2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Functional Description 06/29/07
Broadcom Corporation
Page 1-70 MIPS4380 Processor Core Document 7405-1HDM00-R
DEBUGGING SUPPORT UNIT
The CPU processor provides standard EJTAG support that is in compliant with the MIPS EJTAG 2.0. Basic support includes
a debug mode, run control, single stepping, and software breakpoint instruction (SDBBP). These features allow for the basic
software debug of user and kernel code.
Moreover, the CPU provides a non-intrusive hardware debugging support of two of each of instruction, data, and data value
hardware breakpoints. The hardware instruction breakpoints can be configured to generate a debug exception at any
instruction in the virtual address space. Bit mask values may apply in the address compare. The data breakpoints can be
configured to generate a debug exception on a data transaction, which may be qualified with both virtual address, data value,
size and load/store transaction type. Bit mask value may apply in the address compare, and byte mask may apply in the
data value compare.
In a CMT CPU, the EJTAG functions can only be performed on one TP at a time.
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