Broadcom BCM7405 - Table 1-34: DDR Interface Timing Parameters

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Timing and AC Characteristics 06/29/07
Broadcom Corporation
Page 1-164 DDR Interface Timing Document 7405-1HDM00-R
Table 1-34: DDR Interface Timing Parameters
S.No Parameter Notation Min (ns) Max (ns)
1 Clk Period tCK 2 3
2 Clk high level width tCH TBD –
3 Clk Low level width tCL TBD –
4 RASb output setup time w.r.t clk Ts TBD –
5 CASb output setup time w.r.t clk Ts TBD –
6 WEb output setup time w.r.t clk Ts TBD –
7 CKE output setup time w.r.t clk Ts 1 –
8 Addr[12:0] output setup time w.r.t clk Ts 1 –
9 BA output setup time w.r.t clk Ts 1 –
10 RASb output hold time w.r.t clk Th 1 –
11 CASb output hold time w.r.t clk Th 1 –
12 WEb output hold time w.r.t clk Th 1 –
13 CKE output hold time w.r.t clk Th 1 –
14 Addr[12:0] output hold time w.r.t clk Th 1 –
15 BA output hold time w.r.t clk Th 1 –
16 DQS[7:0] output pulse width Tdpwo 1.9 –
17 DQ[63:0] output setup time w.r.t DQS Ts 0.7 –
18 DQ[63:0] output hold time w.r.t DQS Th 0.7 –
19 DQM[7:0] output setup time w.r.t DQS Ts 0.7 –
20 DQM[7:0] output hold time w.r.t DQS Th 0.7 –
21 Required input data window for reads (DQ[63:0]) Tdv_read 1.2 –
22 Required input dqs pulse width (DQS[7:0]) Tdpwi 1.9 –