2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Functional Description
Broadcom Corporation
Document 7405-1HDM00-R Advanced Video Decoder Page 1-31
XVID
XVID support with the exception of:
• global motion compensation
• 1/4-pel motion compensation
MPEG-1/H.261/H.263
FEATURES
• Error concealment
• SDRAM memory interface for code in and video out
• Five SDRAM clients, three linear, two pixel
• Single-clock design
• Multi-stream support, simultaneous HD + SD support for all protocols
SUPPORTED PICTURE SIZES
• MPEG-2: from 64x16 to 1920x1088
• H.264: from 64x16 to 1920x1088
• VC1: from 64x16 to 1920x1088
• MPEG4/DivX: from 64x16 to 1920x1088
• H.261/H.263: from 64x16 to 1920x1088
• MPEG-1: from 64x16 to 1920x1088
OUTPUT DATA FORMAT
The decoder stores images in a striped format that’s designed to optimize two-dimensional transfers. The images are stored
in 4:2:0 format, with luminance separate from chrominance. Picture buffer management is all under software control. The
decoder’s outer-loop RISC processor passes information about each display frame to an external video feeder, which can
pick it up out of memory.
The optional FGT block average logic writes averages for 8x8 block averages for a frame, and for the 4x8 sums for field 0
in interlaced mode. Each 8x8 average is 8 bits, and is stored in Y0-Y1-Y2-Y3-Cb-Cr order, in MB raster order. The averages
are written starting at the software programmed base address, and are written linearly without any holes.
The 4x8 sums are 16 bits each, and are also written out in Y0-Y1-Y2-Y3-Cb-Cr order. It uses two times as much space as
the averages.
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