2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Functional Description 06/29/07
Broadcom Corporation
Page 1-64 MIPS4380 Processor Core Document 7405-1HDM00-R
MICRO-ARCHITECTURE
• Standard MIPS32 six-stage pipeline
• Multiply-divide unit (MDU)
- Latency of three and four cycles, respectively, for 32x32-multiply and multiply-accumulative operations
- Max issue rate of one 32x32 multiply and multiply accumulate operations every clock
- Divide instructions: 3 to 18 cycles of latency depending on the dividend size
- Each of the TPs has separate set of Hi/Lo registers but they share the MDU execution unit
• Dynamic branch prediction with a 4K-entry branch history table and a 4-entry call-return stack
• Set associative instruction and data caches
- Split I-caches: 2-way set associative, 32 KB for each TP.
- D-cache: 4-way set associative, 64 KB; segment- and page-based write-thru or write-back store policy. The D-cache
is shared by both TPs.
- Both caches: 64-byte line size, LRU (least recently used) replacement algorithm
- A cache store buffer that allows the data cache to be continuously accessed and stored.
• L2 cache holding lines displaced from the instruction and data caches
- 8-way set associative with a capacity of 128 KB, a line size of 64 bytes, and LRU replacement algorithm
- Copyback Gathering: can combine one to four consecutive modified lines to a block to send to the memory
• Readahead cache (RAC) to prefetch and stage the cache lines ahead of cache misses
- 4-way set associative with a capacity of 8 KB, a line size of 256 bytes, and LRU replacement algorithm
- Each TP can independently set up prefetching controls
• Separate write buffers for non-cacheable stores and copybacks
- Stage up to 16 non-cacheable stores, each store can be up to one word
- Stage up to 16 copyback L1 lines
• Low-Latency Memory Bus (LMB) as a high-performance system option
- Direct memory connect
- All the cache misses go through LMB, the rest go through the prevailing system bus
EJTAG DEBUG SUPPORT
• MIPS-standard software debugging with software breakpoints
• Non-intrusive hardware single stepping
• Non-intrusive hardware breakpoints on virtual addresses, physical addresses, and data values: two instruction
breakpoints, two data breakpoints, and two data value breakpoints.
• The EJTAG debugging facility is performed on one TP at a time
To Next Page
Loading...