Broadcom BCM7405 - Memory Controller; Overview

2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Functional Description
Broadcom Corporation
Document 7405-1HDM00-R Memory Controller Page 1-59
MEMORY CONTROLLER
OVERVIEW
The BCM7405 has a 64-bit DDR2 interface that supports all of the functions in the BCM7405, including HD AVC/MPEG/
VC-1 decode, graphics, high-performance CPU, streaming video and audio, SATA, USB Ethernet, and so on. The 64-bit
DDR2 interface can be configured into five different modes—64-bit UMA, 32-bit UMA, 16-bit UMA, 32-/16-bit non-UMA, and
16/16-bit non-UMA depending upon the strap options on the system board. The DDR2 is running up to 400 MHz. The
SDRAM memory controller can support up to 1 GB on the 64-bit UMA configuration.
The BCM7405 includes one primary 64-/32-/16-bit memory controller, which supports UMA configurations, and an optional
32-/16-bit which supports non-UMA configurations. Figure 1-15 on page 1-60 depicts the proposed partitioning for the
BCM7405. This chip has a specific requirement to configure a single 64-bit DDR2 physical interface to following modes:
1 One 64-bit DDR2 interface
2 One 32-bit DDR2 interface
3 One 16-bit DDR2 interface
4 One 32-bit DDR2 interface and one 16-bit DDR2 interface
5 One 16-bit DDR2 interface and another 16-bit DDR2 interface
Assuming that in Modes 4 and 5 the two controllers are independent of each other, Figure 1-15 shows the how the above
five modes are achieved:
• Mode 1 is achieved by setting the mux to use ONLY Memory Controller Core-1 and by programming the Core-1 in 64-bit
mode
• Mode 2 is achieved by setting the mux to use ONLY Memory Controller Core-1 and by programming the Core-1 in 32-bit
mode.
• Mode 3 is achieved by setting the mux to use ONLY Memory Controller Core-1 and by programming the Core-1 in 16-bit
mode.
• Mode 4 is achieved by setting the mux to use the Memory Controller Core-2. Here the Memory Controller Core-1is
programmed in 32-bit mode and Memory Controller Core-2 is programmed in 16-bit mode.
• Mode 5 is achieved by setting the mux to use the Memory Controller Core-2. Here the Memory Controller Core-1 is
programmed in 16-bit mode and Memory Controller Core-2 is programmed in 16-bit mode.
Note that the BCM7405 has two set’s of Address/Control pins to mitigate interface timing issues at 400 MHz. The second
set of Address/Control logic is simply muxed to Memory Controller Core-2 in Modes 4 and 5. For the BCM7405, it is also
assumed that both the memory controller core gets the same clock.