2/24/2008 9T6WP
Preliminary Hardware Data Module BCM7405
06/29/07 Functional Description
Broadcom Corporation
Document 7405-1HDM00-R MIPS4380 Processor Core Page 1-63
MIPS4380 PROCESSOR CORE
OVERVIEW
This section highlights the features of the MIPS CPU architecture. All the application specifics, such as the cache
configurations are also included.
ARCHITECTURE
• Full MIPS32 architecture compliant
- MIPS32 instruction set architecture (ISA)
- MISP32 privileged resource architecture
- MIPS32 MMU with 32-entry TLB
- Odd/even page translation, variable page sizes from 4 KB to 256 MB
- Fully programmable with a set of CP0 registers and instructions
- Byte ordering of operands in either big or little endian configuration
• MIPS32 extended and optional instructions
- IEEE 754 standard floating-point unit supporting single-precision and double-precision
- MIPS16e application-specific extension
- Multiply-accumulate instructions (MADD, MADDU, MSUB, MSUBU)
- Targeted multiply instruction (MUL)
- Count leading zero and one bit-manipulation instructions (CLZ, CLO)
- Conditional move instructions (MOVZ, MOVN)
- Atomic instructions of load-linked (LL) and store-conditional (SC) enhanced for cache sharing by concurrent threads
- PREF instructions with all the hint options
- Cache instructions and line-based locking
- eDSP instructions in SPECIAL2 for 16-bit DSP computation, dual MAC, two pairs of HI/LO special registers, direct
store from Hi/Lo to the memory
• Concurrent multi-threading (CMT)
- Two thread processors (TPs) can simultaneously execute two applications
- Each of the TPs has its own instruction unit, execution unit, register file, MMU, and exception state, but they share
the data cache, level-2 cache, and the rest of system resources.
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