Broadcom BCM7405 - BSC Master; Programmable Queue; Programmable Queue Pointer; Programmable Transfer Delay

2/24/2008 9T6WP
BCM7405 Preliminary Hardware Data Module
Functional Description 06/29/07
Broadcom Corporation
Page 1-78 Peripherals Document 7405-1HDM00-R
• Wraparound Transfer mode—For auto-scanning of serial peripherals (serial ADCs).
• Dual-Access 32-word static RAM
• Programmable Transfer Length—8-bits to 16-bits inclusive
• Programmable Transfer Delay
• Programmable Queue Pointer
Programmable Queue
A programmable queue facilitates the MSPI to perform up to 16 serial transfers without host intervention. Each queue entry
contains all of the information needed by the MSPI to independently complete one serial transfer. This unique feature greatly
reduces Host/MSPI interaction, improving system throughput.
Wraparound Transfer Mode
Wraparound Transfer mode allows automatic, continuous reexecution of the preprogrammed queue entries. Wraparound
simplifies serial peripheral interfaces by automatically and continuously providing the Host with the latest information in the
MSPI RAM. Serial peripherals, in this mode, appear as memory-mapped parallel devices to the Host.
Programmable Transfer Length
The programmable length simplifies interfacing with serial peripherals that require different data lengths. The number of bits
in the transfer is programmable from eight to sixteen bits, inclusive.
Programmable Transfer Delay
The programmable transfer delay length simplifies interfacing with serial peripherals that require a delay time between each
transfer. An inter-transfer delay may be programmed from 32 to 8192 system clocks.
Programmable Queue Pointer
The queue pointer identifies the queue location containing the data for the next serial transfer. The host can change the
location in the queue that is to be transferred next by writing to the queue pointer; otherwise, the pointer increments after
each serial transfer. Segmenting the queue allows the host to support multitasking operations.
BSC MASTER
The BCM7405 includes four BSC master ports. Master clock rate can be selected from the following possibilities based on
internal clock dividers from the 27-MHz clock:
• 390 kHz
• 375 kHz
• 200 kHz
• 187.5 kHz
• 97.5 kHz
• 93.75 kHz
• 50 kHz
• 46.87 kHz
The BSC master interface allows users to access (read/write) data registers of another device with a BSC slave interface
through a SDA (data) and SCL (clock) two-wire bus. Most of required BSC specifications are supported, except for the