REG:2F:0C – EVC_FFR – Frame Filter Rejection Counter
The bits of the EVC_FFR register are described below:
Description of fields within Sub-Register 0x2F:0C – Frame Filter Rejection Counter
EVC_FFR
reg:2F:0C
bits:11–0
Frame Filter Rejection Event Counter. The EVC_FFR field is a 12-bit counter of the frames
rejected by the receive frame filtering function. This is essentially a count of the reporting of
AFFREJ events (in Register file: 0x0F – System Event Status Register).
NB: For this counter to be active, counting needs to be enabled by the setting the EVC_EN bit
in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.7 Sub-Register 0x2F:0E – RX Overrun Error Counter
Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x0E is the RX Overrun Error counter.
REG:2F:0E – EVC_OVR – RX Overrun Error Counter
The bits of the EVC_OVR register are described below:
Description of fields within Sub-Register 0x2F:0C – Frame Filter Rejection Counter
EVC_OVR
reg:2F:0E
bits:11–0
RX Overrun Error Event Counter. The EVC_OVR field is a 12-bit counter of receive overrun
events. This is essentially a count of the reporting of RXOVRR events in Register file: 0x0F –
System Event Status Register. The EVC_OVR will be incremented once for each RX frame
discard that happens while an overrun condition persists.
NB: For this counter to be active, counting needs to be enabled by the setting the EVC_EN bit
in Sub-Register 0x2F:00 – Event Counter Control.
The remaining bits of this register are reserved.
7.2.48.8 Sub-Register 0x2F:10 – SFD Timeout Error Counter
SFD Timeout Error Counter
Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x10 is the SFD Timeout Error counter.
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