decaWave DW1000 - Page 84

DW1000 User Manual
© Decawave Ltd 2017
Version 2.12
Page 84 of 242
Field
Description of fields within Register file: 0x0E – System Event Mask Register
MRXPHD
reg:0E:00
bit:11
Mask receiver PHY header detect event. When MRXPHD is 0 the RXPHD event status bit will
not generate an interrupt. When MRXPHD is 1 and the RXPHD event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MRXPHE
reg:0E:00
bit:12
Mask receiver PHY header error event. When MRXPHE is 0 the RXPHE event status bit will
not generate an interrupt. When MRXPHE is 1 and the RXPHE event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MRXDFR
reg:0E:00
bit:13
Mask receiver data frame ready event. When MRXDFR is 0 the RXDFR event status bit will
not generate an interrupt. When MRXDFR is 1 and the RXDFR event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MRXFCG
reg:0E:00
bit:14
Mask receiver FCS good event. When MRXFCG is 0 the RXFCG event status bit will not
generate an interrupt. When MRXFCG is 1 and the RXFCG event status bit is 1, the hardware
IRQ interrupt line will be asserted to generate an interrupt.
MRXFCE
reg:0E:00
bit:15
Mask receiver FCS error event. When MRXFCE is 0 the RXFCE event status bit will not
generate an interrupt. When MRXFCE is 1 and the RXFCE event status bit is 1, the hardware
IRQ interrupt line will be asserted to generate an interrupt.
MRXRFSL
reg:0E:00
bit:16
Mask receiver Reed Solomon Frame Sync Loss event. When MRXRFSL is 0 the RXRFSL event
status bit will not generate an interrupt. When MRXRFSL is 1 and the RXRFSL event status bit
is 1, the hardware IRQ interrupt line will be asserted to generate an interrupt.
MRXRFTO
reg:0E:00
bit:17
Mask Receive Frame Wait Timeout event. When MRXRFTO is 0 the RXRFTO event status bit
will not generate an interrupt. When MRXRFTO is 1 and the RXRFTO event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MLDEERR
reg:0E:00
bit:18
Mask leading edge detection processing error event. When MLDEERR is 0 the LDEERR event
status bit will not generate an interrupt. When MLDEERR is 1 and the LDEERR event status
bit is 1, the hardware IRQ interrupt line will be asserted to generate an interrupt.
–
reg:0F:00
bit:19
This bit is reserved.
MRXOVRR
reg:0E:00
bit:20
Mask Receiver Overrun event. When MRXOVRR is 0 the RXOVRR event status bit will not
generate an interrupt. When MRXOVRR is 1 and the RXOVRR event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MRXPTO
reg:0E:00
bit:21
Mask Preamble detection timeout event. When MRXPTO is 0 the RXPTO event status bit will
not generate an interrupt. When MRXPTO is 1 and the RXPTO event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MGPIOIRQ
reg:0E:00
bit:22
Mask GPIO interrupt event. When MGPIOIRQ is 0 the GPIOIRQ event status bit will not
generate an interrupt. When MGPIOIRQ is 1 and the GPIOIRQ event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MSLP2INIT
reg:0E:00
bit:23
Mask SLEEP to INIT event. When MSLP2INIT is 0 the SLP2INIT event status bit will not
generate an interrupt. When MSLP2INIT is 1 and the SLP2INITevent status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.
MRFPLLLL
reg:0E:00
bit:24
Mask RF PLL Losing Lock warning event. When MRFPLLLL is 0 the RFPLL_LL event status bit
will not generate an interrupt. When MRFPLLLL is 1 and the RFPLL_LL event status bit is 1,
the hardware IRQ interrupt line will be asserted to generate an interrupt.
MCPLLLL
reg:0E:00
bit:25
Mask Clock PLL Losing Lock warning event. When MCPLLLL is 0 the CLKPLL_LL event status
bit will not generate an interrupt. When MCPLLLL is 1 and the CLKPLL_LL event status bit is 1,
the hardware IRQ interrupt line will be asserted to generate an interrupt.