Description of fields within Register file: 0x0F – System Event Status Register
Preamble detection timeout. This event status bit is set when the preamble detection timeout
occurs. The preamble detection timer is started when the receiver is enabled and begins
preamble hunt. This may begin immediately in the case of issuing an RXENAB command or
after a delay in the case of issuing a RXDLYE command. The preamble detection timeout value
is programmed in Sub-Register 0x27:24 – DRX_PRETOC.
The preamble detection timeout may be useful to save power by turning off the receiver if an
expected response frame does not begin. If a response message is expected with a certain
fixed timing and preamble is not detected at the appropriate time then this is likely to mean
that the response will not come. Reception can thus be aborted early, saving power.
The RXPTO bit is automatically cleared at the next receiver enable. It can also be cleared
explicitly by writing a 1 to it.
GPIO interrupt. The GPIOIRQ event status bit is set when an interrupt condition occurs in the
GPIO block. Various configurations are possible to enable interrupts coming from GPIO input
lines. The GPIO block may need to be interrogated to determine the source of the interrupt if
more than one input line is configured to interrupt. The GPIOIRQ bit is cleared by writing a 1
to it. For details of GPIO programming see Register file: 0x26 – GPIO control and status.
SLP2INIT
reg:0F:00
bit:23
SLEEP to INIT. This event status bit is set is set to indicate that the DW1000 has completed the
activities associated with awaking from SLEEP (or DEEPSLEEP) and is now in the INIT state. This
status bit will NOT activate if the LDE is configured to automatically download on wake up (by
setting the ONW_LLDE bit in Register file 0x2C:00-AON_WCFG ), in this case the CPLOCK status
bit should be used to indicate that wake up has occurred and the DW1000 is in the IDLE state.
RFPLL_LL
reg:0F:00
bit:24
RF PLL Losing Lock. This event status bit is set is set to indicate that the RFPLL is having locking
issues. This should not happen in healthy devices operating in their normal range. Its
occurrence may indicate a bad configuration, a faulty part or a problem in the power or clock
inputs to the device. If this bit is set it may be advisable to turn off the transmitter to avoid
sending signals that are out of regulation. The RFPLL_LL bit is cleared by writing a 1 to it.
CLKPLL_LL
reg:0F:00
bit:25
Clock PLL Losing Lock. This event status bit is set is set to indicate that the system’s digital
clock PLL is having locking issues. This should not happen in healthy devices operating in their
normal range. Its occurrence may indicate a bad configuration, a faulty part or a problem in
the power or clock inputs to the device. If this bit is set it may be advisable to turn off the
transmitter to avoid sending spurious signals. The CLKPLL_LL bit is cleared by writing a 1 to it.
Note: The PLLLDT bit in Register file 0x24:00 –EC_CTRL should be set to ensure reliable
operation of this CLKPLL_LL bit.
Receive SFD timeout. This event status bit is set when the SFD detection timeout occurs. The
SFD detection timeout starts running as soon as preamble is detected. If the SFD sequence is
not detected before the timeout period expires then the timeout will act to abort the
reception currently in progress. The period of the SFD detection timeout is in Sub-Register
0x27:20 – DRX_SFDTOC. By default this has a value of 4096+64 representing the longest
possible preamble and SFD. Where it is known that a shorter preamble and SFD are being
employed this value can be reduced. The RXSFDTO event status bit can be cleared explicitly by
writing a 1 to it. It is also automatically cleared by the next receiver enable, including those
caused by the RXAUTR auto-re-enable. SFD timeout events are also counted in Sub-Register
0x2F:10 – SFD Timeout Error Counter, assuming that counting is enabled by the EVC_EN bit in
Sub-Register 0x2F:00 – Event Counter Control.
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