Emerson Affinity - Figure 11-31 SM-I;O PELV Digital Input Logic Diagram; Figure 11-32 SM-I;O PELV Relay Logic Diagram; Figure 11-33 SM-I;O PELV Analog Input Logic Diagram

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202 Affinity User Guide
www.controltechniques.com Issue Number: 5
Figure 11-31 SM-I/O PELV digital input logic diagram
Figure 11-32 SM-I/O PELV relay logic diagram
Figure 11-33 SM-I/O PELV analog input logic diagram
??.??
Any
unprotected
bit
parameter
??.??
X.25
x(-1)
X.15X.05
T7 digital input 5
T7 digital
input 5 state
T7 digital
input 5 invert
T7 digital input 5
destination
Relay 2
X.17
Relay 1
0.XX
0.XX
Key
Read-write
(RW)
parameter
Read-only (RO)
parameter
Input
terminals
Output
terminals
The parameters are all shown at their default setting
X.41
Analog
input 1
scaling
??.??
Any
unprotected
variable
parameter
??.??
X.43
Analog
input 1
destination
x(-1)
X.42
Analog input 1
invert
X.40
Analog input 1
Analog input
1 level
8
9
+
_
X.38
Analog
input 1
mode selector