GE MiCOM P40 - Page 878

Appendix B -Settings and Signals
P446SV
B132
P446SV-TM-EN-1
MENU TEXT COL ROW DEFAULT SETTING AVAILABLE OPTIONS
DESCRIPTION
Live Bus 2 48 89 32
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus 2 is considered Live with voltage above this setting.
Dead Bus 2 48 8A 13
From 5 to 132 in steps of 0.5
[Courier Number (voltage)]
Bus 2 is considered Dead with voltage below this setting.
CS UV 48 8B 54
From 5 to 120 in steps of 0.5
[Courier Number (voltage)]
Check Synch Undervoltage setting decides that System Check Synchronism logic for CB1 will be blocked if V< is one of the selected options in
setting CB1 CS Volt.Blk (48 8 E), and either line or bus voltage is below this setting.
System Check Synchronism for CB2 will be blocked if V< is one of the selected options in setting CB2 CS Volt. Blk (48 9 C), and either line or bus
voltage is below this setting.
CS OV 48 8C 130
From 60 to 200 in steps of 0.5
[Courier Number (voltage)]
Check Synch Overvoltage setting decides that System Check Synchronism logic for CB1 is blocked if V> is one of the selected options in
setting CB1 CS Volt.Blk (48 8 E), and either line or bus voltage is above this setting.
System Check Synchronism for CB2 is blocked if V> is one of the selected options in setting CB2 CS Volt. Blk (48 9 C), and either line or bus
voltage is above this setting.
Sys Checks CB1 48 8D Disabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable both stages of system checks for reclosing CB1
If Sys Checks CB1 is set to Disabled, all other menu settings associated with synchronism checks for CB1 become invisible, and a DDB (880)
signal SChksInactiveCB1 is set.
CB1 CS Volt. Blk 48 8E V<
None
V<
V>
Vdiff>
V< and V>
V< and Vdiff>
V> and Vdiff>
V< V> and Vdiff>
[Indexed String]
Setting to determine which, if any, conditions should block synchronism check for CB1 (undervoltage V<, overvoltage V>, and/or voltage
differential Vdiff etc) for the line and bus voltages.
CB1 CS1 Status 48 8F Enabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable the stage 1 synchronism check elements for auto-reclosing and manual closing CB1.
CB1 CS1 Angle 48 90 20
From 0 to 90 in steps of 1
[Courier Number (angle)]
Maximum permitted phase angle between Line and Bus 1 voltages for first stage synchronism check element to reclose CB1.
CB1 CS1 VDiff 48 91 6.5
From 1 to 120 in steps of 0.5
[Courier Number (voltage)]
Check Synch Voltage differential setting decides that stage 1 System Check Synchronism logic for CB1 is blocked if Vdiff> is one of the
selected options in setting CB1 CS Volt. Blk (48 8 E), and voltage magnitude difference between line and bus 1 voltage is above this setting.
CB1 CS1 SlipCtrl 48 92 Enabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable blocking of synchronism check stage 1 for reclosing CB1 by excessive frequency difference (slip) between line
and bus voltages
(refer to setting CB1 CS1 SlipFreq).
CB1 CS1 SlipFreq 48 93 0.05
From 0.005 to 2 in steps of 0.005
[Courier Number (frequency)]
If CB1 CS1 SlipCtrl is enabled, synchronism check stage 1 is blocked for reclosing CB1 if measured frequency difference between line and bus
voltages is greater than this setting.
CB1 CS2 Status 48 94 Disabled
Disabled
Enabled
[Indexed String]
Setting to enable or disable the stage 2 synchronism check elements for auto-reclosing and manual closing CB1.
CB1 CS2 Angle
48
95
20
From 0 to 90 in steps of 1