Appendix B -Settings and Signals
MENU TEXT COL ROW DEFAULT SETTING AVAILABLE OPTIONS
DESCRIPTION
Maximum permitted phase angle between Line and Bus 1 voltages for second stage synchronism check element to reclose CB1
CB1 CS2 VDiff 48 96 6.5
From 1 to 120 in steps of 0.5
[Courier Number (voltage)]
Check Synch Voltage differential setting decides that stage 2 System Check Synchronism logic for CB1 is blocked if Vdiff> is one of the
selected options in setting CB1 CS Volt.Blk (48 8 E), and voltage magnitude difference between line and bus 1 voltage is above this setting.
CB1 CS2 SlipCtrl 48 97 Enabled
Enabled
Setting to enable or disable blocking of synchronism check stage 2 for reclosing CB1 by excessive frequency difference (slip) between line
and bus voltages (refer to setting CB1 CS2 SlipFreq)
CB1 CS2 SlipFreq 48 98 0.05
From 0.005 to 2 in steps of 0.005
[Courier Number (frequency)]
If CB1 CS2 SlipCtrl is enabled, synchronism check stage 2 is blocked for reclosing CB1 if measured frequency difference between line and bus
voltages is greater than this setting.
CB1 CS2 Adaptive 48 99 Disabled
Enabled
Setting to enable or disable Adaptive CB closing with System Check Synchronism stage 2 closing for CB1: logic uses set CB1 CI Time to issue
CB1 close command at such a time that the predicted phase angle difference when CB1 main contacts touch is as close as possible to 0
degrees. If Adaptive closing is disabled, the logic issues CB1 close command as soon as phase angle comes within set limit at CB1 CS2 Angle
CB1 Cl Time 48 9A 0.05
From 0.01 to 0.5 in steps of 0.001
[Courier Number (time-seconds)]
This sets CB1 closing time, from receipt of CB1 close command until main contacts touch.
Sys Checks CB2 48 9B Disabled
Disabled
Enabled
Setting to enable or disable both stages of system checks for reclosing CB2.
If Sys Checks CB2 is set to Disabled, all other menu settings associated with synchronism checks for CB2 become invisible, and a DDB (1484)
signal SChksInactiveCB2 is set.
CB2 CS Volt. Blk 48 9C V<
V<
V>
Vdiff>
V< and V>
V< and Vdiff>
V> and Vdiff>
V< V> and Vdiff>
Setting to determine which, if any, conditions should block synchronism check for CB2 (undervoltage V<, overvoltage V>, and/or voltage
differential Vdiff etc) for the line and bus voltages.
CB2 CS1 Status 48 9D Enabled
Enabled
Setting to enable or disable the stage 1 synchronism check elements for auto-reclosing and manual closing CB2.
CB2 CS1 Angle 48 9E 20
From 0 to 90 in steps of 1
[Courier Number (angle)]
Maximum permitted phase angle between Line and Bus 2 voltages for first stage synchronism check element to reclose CB2.
CB2 CS1 VDiff 48 9F 6.5
From 1 to 120 in steps of 0.5
[Courier Number (voltage)]
Check Synch Voltage differential setting decides that stage 1 System Check Synchronism logic for CB2 is blocked if Vdiff> is one of the
selected options in setting CB2 CS Volt. Blk (48 9C), and voltage magnitude difference between line and bus 2 voltage is above this setting.
CB2 CS1 SlipCtrl 48 A0 Enabled
Enabled
Setting to enable or disable blocking of synchronism check stage 1 for reclosing CB2 by excessive frequency difference (slip) between line
and bus voltages (refer to setting CB2 CS1 SlipFreq).
CB2 CS1 SlipFreq 48 A1 0.05
From 0.005 to 2 in steps of 0.005
[Courier Number (frequency)]
If CB2 CS1 SlipCtrl is enabled, synchronism check stage 1 is blocked for reclosing CB2 if measured frequency difference between line and bus
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