3.1.2 Inhibit Autoreclose Input 254
3.1.3 Block Autoreclose Input 254
3.1.4 Reset Lockout Input 255
3.1.5 Pole Discrepancy Input 255
3.1.6 External Trip Indication 255
3.2 Autoreclose Logic Inputs 255
3.2.1 Trip Initiation Signals 255
3.2.2 Circuit Breaker Status Inputs 255
3.2.3 System Check Signals 255
3.3 Autoreclose Logic Outputs 255
3.4 Autoreclose Operating Sequence 256
3.4.1 AR Timing Sequence - Transient Fault 256
3.4.2 AR Timing Sequence - Evolving/Permanent Fault 256
3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 257
3.4.4 AR Timing Sequence - Transient Fault Dual CB 257
3.4.5 AR Timing Sequence - Evolving/Permanent Fault Dual CB 258
3.4.6 AR Timing Sequence - Persistent Fault 259
4 Autoreclose System Map 261
4.1 Autoreclose System Map Diagrams 263
4.2 Autoreclose Internal Signals 272
4.3 Autoreclose DDB Signals 277
5 Logic Modules 289
5.1 Circuit Breaker Status Monitor 289
5.1.1 CB State Monitor 290
5.2 Circuit Breaker Open Logic 290
5.2.1 Circuit Breaker Open Logic Diagram 291
5.3 Circuit Breaker in Service Logic 291
5.3.1 Circuit Breaker in Service Logic Diagram 292
5.4 Autoreclose Enable Logic 292
5.4.1 Autoreclose Enable Logic Diagram 292
5.5 Autoreclose Leader/Follower 292
5.5.1 Leader/Follower CB Selection Logic Diagram 293
5.5.2 Leader Follower Logic Diagram 294
5.6 Autoreclose Modes 295
5.6.1 Single-Phase and Three-Phase Autoreclose 295
5.6.2 Autoreclose Modes Enable Logic Diagram 296
5.7 AR Force Three-Phase Trip Logic 297
5.7.1 Force Three-Phase Trip Logic Diagram 297
5.8 Autoreclose Initiation Logic 298
5.8.1 Autoreclose Initiation Logic Diagram 299
5.8.2 Autoreclose Trip Test Logic Diagram 299
5.8.3 External Trip Logic Diagram for CB1 300
5.8.4 External Trip Logic Diagram for CB2 301
5.8.5 Protection Reoperation and Evolving Fault Logic Diagram 302
5.8.6 Fault Memory Logic Diagram 302
5.9 Autoreclose In Progress 302
5.9.1 Autoreclose In Progress Logic Diagram for CB1 303
5.9.2 Autoreclose In Progress Logic Diagram for CB2 304
5.10 Sequence Counter 304
5.10.1 Autoreclose Sequence Counter Logic Diagram 305
5.11 Autoreclose Cycle Selection 305
5.11.1 Single Phase Autoreclose Cycle Selection Logic Diagram 306
5.11.2 3-phase Autoreclose Cycle Selection 307
5.12 Dead Time Control 307
5.12.1 Dead Time Start Enable Logic Diagram 308
5.12.2 Single-phase Leader Dead Time Logic Diagram 309
5.12.3 3-phase Leader Dead Time Logic Diagram 310
5.12.4 Follower Enable Logic Diagram 311
P446SV Contents
P446SV-TM-EN-1 vii