GE PACSystems RX7i

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Chapter 5. Communications

186 PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD

10Base-T/100Base-Tx Port Pin Assignments

Pin assignments are the same for the RX3i and RX7i embedded Ethernet ports.

Pin Number

Signal

Description

TD+

Transmit Data +

TD-

Transmit Data -

RD+

Receive Data +

No connection

RD-

Receive Data -

No connection

Recovering a Lost IP Address

See Establishing Initial Ethernet Communications, Section 3.4.1.

Main Page

Default Chapter4
- Table of Contents4
Table of Figures9
Chapter 1 Introduction12
Revisions in this Manual13
Pacsystems Control System Overview16
- Programming and Configuration16
- Process Systems16
- Pacsystems CPU Models17
Rx3I Overview19
Rx7I Overview22
Rsti-EP Overview23
Migrating Series 90 Applications to Pacsystems24
Documentation25
Chapter 2 CPU Features & Specifications28
Common CPU Features29
- Features Shared by All Pacsystems CPU Models29
- Features Shared by Certain Pacsystems CPU Models30
- Firmware Storage in Flash Memory31
- Operation, Protection, and Module Status31
- Ethernet Global Data31
- Embedded PROFINET Controller32
- Figure 1: Configuring an Embedded PROFINET Controller32
- Opc Ua33
- Removable Data Storage Devices (Rdsds)34
- CPU Over-Temperature Monitoring and Behavior39
Rx3I CPU Features and Specifications40
- Cpe40046
- Figure 2: CPE400 Front View and Features46
- Figure 3: CPE400 Underside Ports & Connectors50
- Figure 4: CPE400 Micro-SD & USB Pinouts52
- Figure 5: Typical Field Agent Application56
- Figure 6: Login to Predix57
- Figure 7: Predix Change Password58
- Figure 8: Log Service Page58
- Figure 9: Technician Console, Network Configuration Page59
- Figure 10: Enter Proxy Server Address60
- Figure 11: Test Connection60
- Figure 12: Technician Console, Time Sync Configuration61
- Figure 13: LAN3 Interconnects for Hot Standby Redundancy64
- Figure 14: Display Port Connector66
- Figure 15: Location of RTC Battery on CPE40068
- Figure 16: DIN-Rail Mount Bracket Assembly CPE40071
- Figure 17: Panel-Mount Bracket Assembly CPE40071
- Cpe33072
- Figure 18: CPE330 Front View & Features72
- Figure 19: CPE330 RUN/STOP Switch and RDSD Switches74
- Figure 20: Location and Orientation of Real-Time Clock Battery in CPE33077
- CPE302, CPE305 and CPE31081
- Figure 21: IC695CPE302/CPE305 Front View81
- Figure 22: IC695CPE310 Front View81
- Figure 23: External Features of CPE302/CPE30583
- Figure 24: External Features of CPE31083
- Figure 25: Accessing Real-Time Clock Battery (CPE302, CPE305 and CPE310)86
- Figure 26: Sample Tool for Coin Battery Extraction87
- CPU315 and CPU320/CRU32090
- Figure 27: IC695CPU320 Front View90
- Cpu31093
- Figure 28: IC695CPU310 Front View93
Rx7I CPU Features and Specifications95
- CPE030/CRE030 and CPE040/CRE040100
- Figure 29: CPE040 Front View100
- CPE010, CPE020 and CRE020102
- Figure 30: CPE010 Front View102
- Rx7I Embedded Ethernet Interface104
Rsti-EP CPU Features and Specifications109
- Cpe100/Cpe115112
- Figure 31: CPE100/CPE115 Front, Top and Bottom Views and Features112
- Figure 32: CPE100/CPE115 Membrane Pushbutton and Module Status Leds114
- Figure 33: State Diagram for CPE100/CPE115 Run/Stop Operation114
- Figure 34: Typical Multi-Tier LAN Application (Star/Bus Topology)117
- Figure 35: Typical Multi-Tier LAN Application (Ring Topology)117
Chapter 3 CPU Configuration120
Configuring the CPU121
- Figure 36: PME Expansion of Pacsystems Target121
Configuration Parameters122
- Settings Parameters122
- Modbus TCP Address Map125
- Sntp126
- Time127
- Scan Parameters128
- Memory Parameters131
- Fault Parameters134
- Redundancy Parameters (Redundancy Cpus Only)136
- Transfer List136
- COM1 and COM2 Parameters137
- Scan Sets Parameters141
- Power Consumption Parameters141
- Access Control142
- OPC UA Parameters143
Storing (Downloading) Hardware Configuration144
- Figure 37: Downloading Hardware Config to CPU144
Configuring the Embedded Ethernet Interface145
- Figure 38: Selecting Embedded Ethernet for Configuration145
Chapter 4 CPU Operation150
CPU Sweep151
- Parts of the CPU Sweep152
- Figure 40: Major Phases of a Typical CPU Sweep152
- CPU Sweep Modes155
- Figure 41: Typical Sweeps in Normal Sweep Mode155
- Figure 42: Typical Sweeps in Constant Sweep Mode156
Program Scheduling Modes157
- Figure 43: Typical Sweeps in Constant Window Mode157
Window Modes158
Data Coherency in Communications Windows159
Run/Stop Operations160
- CPU STOP Modes161
- Figure 44: CPU Sweep in Stop-I/O Disabled and Stop-I/O Enabled Modes161
- STOP-To-RUN Mode Transition163
- RUN/STOP Switch Operation163
Flash Memory Operation164
Logic/Configuration Source and CPU Operating Mode at Power-Up165
- CPU Mode When Memory Not Preserved/Power-Up Source Is Flash166
- CPU Mode When Memory Preserved167
Clocks and Timers168
- Elapsed Time Clock168
- Time-Of-Day Clock169
- Watchdog Timer170
System Security172
- Passwords and Privilege Levels - Legacy Mode173
- OEM Protection - Legacy Mode175
- Enhanced Security for Passwords and OEM Protection176
- Legacy/Enhanced Security Comparison177
Pacsystems I/O System178
- I/O Configuration179
- Genius I/O181
- I/O System Diagnostic Data Collection183
Power-Up and Power-Down Sequences185
- Power-Up Sequence185
- Power-Down Sequence186
- Power Cycle Operation with an Energy Pack187
- Retention of Data Memory Across Power Failure190
Chapter 5 Communications192
Ethernet Communications193
- Embedded Ethernet Interface193
- Figure 45: CPE330 Overlapping Local IP Subnet Example194
- Figure 46: Expected Response Path195
- Figure 47: Actual Response Path195
- Ethernet Interface Modules198
Serial Communications199
- Serial Port Communications Capabilities199
- Configurable STOP Mode Protocols201
- Serial Port Pin Assignments202
- Figure 48: COM1 Port CPE400203
- Serial Port Electrical Isolation206
- Serial Cable Lengths and Shielding207
- Serial Port Baud Rates208
Series 90-70 Communications and Intelligent Option Modules209
- Communications Coprocessor Module (CMM)209
- Programmable Coprocessor Module (PCM)210
- DLAN/DLAN+ (Drives Local Area Network) Interface211
Chapter 6 Serial I/O, SNP & RTU Protocols212
Configuring Serial Ports Using COMMREQ Function 65520213
- COMMREQ Function Example213
- Timing213
- Sending Another COMMREQ to the same Port213
- Invalid Port Configuration Combinations214
- COMMREQ Command Block Parameter Values215
- Example COMMREQ Command Blocks for Serial Port Setup Function216
Serial I/O Protocol219
- Calling Serial I/O Commreqs from the CPU Sweep219
- Compatibility219
- Status Word for Serial I/O Commreqs219
- Serial I/O COMMREQ Commands221
- Overlapping Commreqs222
- Initialize Port Function (4300)223
- Set up Input Buffer Function (4301)224
- Flush Input Buffer Function (4302)225
- Read Port Status Function (4303)226
- Write Port Control Function (4304)228
- Cancel COMMREQ Function (4399)229
- Autodial Function (4400)230
- Write Bytes Function (4401)232
- Read Bytes Function (4402)233
- Read String Function (4403)235
RTU Slave Protocol237
- Message Format238
- Figure 49: RTU Message Transactions238
- Figure 50: RTU Read Output Table Example241
- Cyclic Redundancy Check (CRC)243
- RTU Message Descriptions247
- Figure 53: RTU Read Input Table Message Format248
- Figure 54: RTU Read Registers Message Format249
- Figure 55: RTU Read Analog Inputs Message Format250
- Figure 56: RTU Force Single Output Message Format251
- Figure 57: RTU Preset Single Register Message Format252
- Figure 58: RTU Read Exception Status Message Format253
- Figure 59: RTU Loopback/Maintenance Message Format254
- Figure 60: RTU Force Multiple Outputs Message Format256
- Figure 61: RTU Preset Multiple Registers Message Format257
- Figure 62: RTU Report Device Type Message Format258
- Figure 63: RTU Read Scratch Pad Memory Message Format262
- RTU Scratch Pad263
- Communication Errors264
- RTU Slave/Snp Slave Operation with Programmer Attached267
SNP Slave Protocol268
- Permanent Datagrams268
- Communication Requests (Commreqs) for SNP268
Appendix A Performance Data270
Boolean Execution Times271
- A-1.1 Boolean Execution Measurements (Ms Per 1000 Boolean Executions)271
Instruction Timing272
- Overview272
- A-2.2 PLC Version Information273
- Rx3I & Rsti-EP Instruction Times274
- Rx7I Instruction Times275
Overhead Sweep Impact Times286
- A-3.1 Base Sweep Times287
- A-3.2 What the Sweep Impact Tables Contain289
- A-3.3 Programmer Sweep Impact Times290
- A-3.4 I/O Scan and I/O Fault Sweep Impact291
- Ethernet Global Data Sweep Impact298
- EGD Sweep Impact for Embedded Ethernet Interface on Rx3I & Rsti-EP CPE Models301
- A-3.7 Sweep Impact of Intelligent Option Modules305
- A-3.8 I/O Interrupt Performance and Sweep Impact308
- Figure 65: Interrupt Execution Considerations309
- A-3.9 Timed Interrupt Performance311
- A-3.10 Example of Predicted Sweep Time Calculation312
Appendix B User Memory Allocation314
Items that Count against User Memory315
User Program Memory Usage316
- B-2.1 %L and %P Program Memory316
- B-2.2 Program Logic and Overhead316

GE PACSystems RX7i - Page 197

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