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PACSystems RX7i
GE PACSystems RX7i Reference Manual
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Chapter 2
.
CPU Features
& Specifications
GFK
-2222AD
April 2018
55
Display Port
The Display port is n
ot functional at tim
e of publicat
ion.
The
Display
Po
rt
is
a
DP++
video
port
located
on
the
underside
of
the
CPE440
(Figure
3).
It
provides
signals
for connecting a
suitable monitor or vid
eo adapter. Pin
outs for the Display
Port (Figure
14
) a
re:
Pins
Signal Name
1/3
TxD0+/-
4/6
TxD1+/-
7/9
TxD2+/-
10/12
TxD3+/-
13
AUXSEL
15
CLK/AUX+
17
DAT/AUX-
18
HTPLG
14
NC
20
DP_VCC
43
2, 5, 8, 11, 16, 19
GND
Figure
14
: Displa
y Port Connector
43
DP_VCC is limited to 720mA by an electron
ic fuse.
However, for normal operation do not exceed 500mA at this pin.
65
67
Table of Contents
Default Chapter
4
Table of Contents
4
Table of Figures
9
Chapter 1 Introduction
12
Revisions in this Manual
13
Pacsystems Control System Overview
16
Programming and Configuration
16
Process Systems
16
Pacsystems CPU Models
17
Rx3I Overview
19
Rx7I Overview
22
Rsti-EP Overview
23
Migrating Series 90 Applications to Pacsystems
24
Documentation
25
Chapter 2 CPU Features & Specifications
28
Common CPU Features
29
Features Shared by All Pacsystems CPU Models
29
Features Shared by Certain Pacsystems CPU Models
30
Firmware Storage in Flash Memory
31
Operation, Protection, and Module Status
31
Ethernet Global Data
31
Embedded PROFINET Controller
32
Figure 1: Configuring an Embedded PROFINET Controller
32
Opc Ua
33
Removable Data Storage Devices (Rdsds)
34
CPU Over-Temperature Monitoring and Behavior
39
Rx3I CPU Features and Specifications
40
Cpe400
46
Figure 2: CPE400 Front View and Features
46
Figure 3: CPE400 Underside Ports & Connectors
50
Figure 4: CPE400 Micro-SD & USB Pinouts
52
Figure 5: Typical Field Agent Application
56
Figure 6: Login to Predix
57
Figure 7: Predix Change Password
58
Figure 8: Log Service Page
58
Figure 9: Technician Console, Network Configuration Page
59
Figure 10: Enter Proxy Server Address
60
Figure 11: Test Connection
60
Figure 12: Technician Console, Time Sync Configuration
61
Figure 13: LAN3 Interconnects for Hot Standby Redundancy
64
Figure 14: Display Port Connector
66
Figure 15: Location of RTC Battery on CPE400
68
Figure 16: DIN-Rail Mount Bracket Assembly CPE400
71
Figure 17: Panel-Mount Bracket Assembly CPE400
71
Cpe330
72
Figure 18: CPE330 Front View & Features
72
Figure 19: CPE330 RUN/STOP Switch and RDSD Switches
74
Figure 20: Location and Orientation of Real-Time Clock Battery in CPE330
77
CPE302, CPE305 and CPE310
81
Figure 21: IC695CPE302/CPE305 Front View
81
Figure 22: IC695CPE310 Front View
81
Figure 23: External Features of CPE302/CPE305
83
Figure 24: External Features of CPE310
83
Figure 25: Accessing Real-Time Clock Battery (CPE302, CPE305 and CPE310)
86
Figure 26: Sample Tool for Coin Battery Extraction
87
CPU315 and CPU320/CRU320
90
Figure 27: IC695CPU320 Front View
90
Cpu310
93
Figure 28: IC695CPU310 Front View
93
Rx7I CPU Features and Specifications
95
CPE030/CRE030 and CPE040/CRE040
100
Figure 29: CPE040 Front View
100
CPE010, CPE020 and CRE020
102
Figure 30: CPE010 Front View
102
Rx7I Embedded Ethernet Interface
104
Rsti-EP CPU Features and Specifications
109
Cpe100/Cpe115
112
Figure 31: CPE100/CPE115 Front, Top and Bottom Views and Features
112
Figure 32: CPE100/CPE115 Membrane Pushbutton and Module Status Leds
114
Figure 33: State Diagram for CPE100/CPE115 Run/Stop Operation
114
Figure 34: Typical Multi-Tier LAN Application (Star/Bus Topology)
117
Figure 35: Typical Multi-Tier LAN Application (Ring Topology)
117
Chapter 3 CPU Configuration
120
Configuring the CPU
121
Figure 36: PME Expansion of Pacsystems Target
121
Configuration Parameters
122
Settings Parameters
122
Modbus TCP Address Map
125
Sntp
126
Time
127
Scan Parameters
128
Memory Parameters
131
Fault Parameters
134
Redundancy Parameters (Redundancy Cpus Only)
136
Transfer List
136
COM1 and COM2 Parameters
137
Scan Sets Parameters
141
Power Consumption Parameters
141
Access Control
142
OPC UA Parameters
143
Storing (Downloading) Hardware Configuration
144
Figure 37: Downloading Hardware Config to CPU
144
Configuring the Embedded Ethernet Interface
145
Figure 38: Selecting Embedded Ethernet for Configuration
145
Establishing Initial Ethernet Communications
146
Setting a Temporary IP Address
148
Figure 39: Set Temporary IP Address
148
Chapter 4 CPU Operation
150
CPU Sweep
151
Parts of the CPU Sweep
152
Figure 40: Major Phases of a Typical CPU Sweep
152
CPU Sweep Modes
155
Figure 41: Typical Sweeps in Normal Sweep Mode
155
Figure 42: Typical Sweeps in Constant Sweep Mode
156
Program Scheduling Modes
157
Figure 43: Typical Sweeps in Constant Window Mode
157
Window Modes
158
Data Coherency in Communications Windows
159
Run/Stop Operations
160
CPU STOP Modes
161
Figure 44: CPU Sweep in Stop-I/O Disabled and Stop-I/O Enabled Modes
161
STOP-To-RUN Mode Transition
163
RUN/STOP Switch Operation
163
Flash Memory Operation
164
Logic/Configuration Source and CPU Operating Mode at Power-Up
165
CPU Mode When Memory Not Preserved/Power-Up Source Is Flash
166
CPU Mode When Memory Preserved
167
Clocks and Timers
168
Elapsed Time Clock
168
Time-Of-Day Clock
169
Watchdog Timer
170
System Security
172
Passwords and Privilege Levels - Legacy Mode
173
OEM Protection - Legacy Mode
175
Enhanced Security for Passwords and OEM Protection
176
Legacy/Enhanced Security Comparison
177
Pacsystems I/O System
178
I/O Configuration
179
Genius I/O
181
I/O System Diagnostic Data Collection
183
Power-Up and Power-Down Sequences
185
Power-Up Sequence
185
Power-Down Sequence
186
Power Cycle Operation with an Energy Pack
187
Retention of Data Memory Across Power Failure
190
Chapter 5 Communications
192
Ethernet Communications
193
Embedded Ethernet Interface
193
Figure 45: CPE330 Overlapping Local IP Subnet Example
194
Figure 46: Expected Response Path
195
Figure 47: Actual Response Path
195
Ethernet Interface Modules
198
Serial Communications
199
Serial Port Communications Capabilities
199
Configurable STOP Mode Protocols
201
Serial Port Pin Assignments
202
Figure 48: COM1 Port CPE400
203
Serial Port Electrical Isolation
206
Serial Cable Lengths and Shielding
207
Serial Port Baud Rates
208
Series 90-70 Communications and Intelligent Option Modules
209
Communications Coprocessor Module (CMM)
209
Programmable Coprocessor Module (PCM)
210
DLAN/DLAN+ (Drives Local Area Network) Interface
211
Chapter 6 Serial I/O, SNP & RTU Protocols
212
Configuring Serial Ports Using COMMREQ Function 65520
213
COMMREQ Function Example
213
Timing
213
Sending Another COMMREQ to the same Port
213
Invalid Port Configuration Combinations
214
COMMREQ Command Block Parameter Values
215
Example COMMREQ Command Blocks for Serial Port Setup Function
216
Serial I/O Protocol
219
Calling Serial I/O Commreqs from the CPU Sweep
219
Compatibility
219
Status Word for Serial I/O Commreqs
219
Serial I/O COMMREQ Commands
221
Overlapping Commreqs
222
Initialize Port Function (4300)
223
Set up Input Buffer Function (4301)
224
Flush Input Buffer Function (4302)
225
Read Port Status Function (4303)
226
Write Port Control Function (4304)
228
Cancel COMMREQ Function (4399)
229
Autodial Function (4400)
230
Write Bytes Function (4401)
232
Read Bytes Function (4402)
233
Read String Function (4403)
235
RTU Slave Protocol
237
Message Format
238
Figure 49: RTU Message Transactions
238
Figure 50: RTU Read Output Table Example
241
Cyclic Redundancy Check (CRC)
243
RTU Message Descriptions
247
Figure 53: RTU Read Input Table Message Format
248
Figure 54: RTU Read Registers Message Format
249
Figure 55: RTU Read Analog Inputs Message Format
250
Figure 56: RTU Force Single Output Message Format
251
Figure 57: RTU Preset Single Register Message Format
252
Figure 58: RTU Read Exception Status Message Format
253
Figure 59: RTU Loopback/Maintenance Message Format
254
Figure 60: RTU Force Multiple Outputs Message Format
256
Figure 61: RTU Preset Multiple Registers Message Format
257
Figure 62: RTU Report Device Type Message Format
258
Figure 63: RTU Read Scratch Pad Memory Message Format
262
RTU Scratch Pad
263
Communication Errors
264
RTU Slave/Snp Slave Operation with Programmer Attached
267
SNP Slave Protocol
268
Permanent Datagrams
268
Communication Requests (Commreqs) for SNP
268
Appendix A Performance Data
270
Boolean Execution Times
271
A-1.1 Boolean Execution Measurements (Ms Per 1000 Boolean Executions)
271
Instruction Timing
272
Overview
272
A-2.2 PLC Version Information
273
Rx3I & Rsti-EP Instruction Times
274
Rx7I Instruction Times
275
Overhead Sweep Impact Times
286
A-3.1 Base Sweep Times
287
A-3.2 What the Sweep Impact Tables Contain
289
A-3.3 Programmer Sweep Impact Times
290
A-3.4 I/O Scan and I/O Fault Sweep Impact
291
Ethernet Global Data Sweep Impact
298
EGD Sweep Impact for Embedded Ethernet Interface on Rx3I & Rsti-EP CPE Models
301
A-3.7 Sweep Impact of Intelligent Option Modules
305
A-3.8 I/O Interrupt Performance and Sweep Impact
308
Figure 65: Interrupt Execution Considerations
309
A-3.9 Timed Interrupt Performance
311
A-3.10 Example of Predicted Sweep Time Calculation
312
Appendix B User Memory Allocation
314
Items that Count against User Memory
315
User Program Memory Usage
316
B-2.1 %L and %P Program Memory
316
B-2.2 Program Logic and Overhead
316
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GE PACSystems RX7i Specifications
General
Brand
GE
Model
PACSystems RX7i
Category
Controller
Language
English
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