94
CPU 0 OCP card slot configuration menu;
Socket 0 PcieBr3D02F0 – Port 3C
CPU 0 is linked to the configuration menu of the PCH upstream channel;
Socket1 Configuration
IOU0 (IIO PCIe Br1)
Control CPU 1 riser 3 x16 PCIE branch options;
IOU1 (IIO PCIe Br2)
Control CPU 1 riser 2 x16 PCIE branch options;
IOU2 (IIO PCIe Br3)
Control the PCIE branch options of CPU1 Slimline 1 and Slimline 2;
Socket 1 PcieBr0D00F0 – Port 0
Unused;
Socket 1 PcieBr1D00F0 – Port 1A
CPU 1 riser 3 x16 slot configuration menu;
Socket 1 PcieBr2D00F0 – Port 2A
CPU 1 riser 2 x16 slot configuration menu;
Socket 1 PcieBr3D00F0 – Port 3A
CPU1 Slimline 1 slot configuration menu;
Socket 1 PcieBr3D02F0 – Port 3C
CPU1 Slimline 2 slot configuration menu;
5.2.31 Advanced Power Management Configuration
Figure 5- 32
CPU P State Control
CPU P state control setting submenu;
Hardware PM State Control