Error Reporting and Handling Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
144
5.2.2.3 Processor Bus Error
The BIOS enables the error correction and detection capabilities of the processors by setting
appropriate bits in the processor model specific register (MSR) and the appropriate bits in the
chipset.
In the case of unrecoverable errors on the host processor bus, proper execution of the SMI
handler cannot be guaranteed and the handler cannot be relied upon to log such conditions.
The handler records the error to the system event log only if the system has not experienced a
catastrophic failure that compromises the integrity of the handler.
5.2.2.4 Memory Bus Error
The hardware is programmed to generate an SMI on correctable data errors in the memory
array. The SMI handler records the error and the FBDIMM location to the system event log.
Uncorrectable errors in the memory array are mapped to SMI because the BMC cannot
determine the location of the faulty FBDIMM. The uncorrectable errors may have corrupted the
contents of SMRAM. The SMI handler will log the failing FBDIMM number to the BMC if the
SMRAM contents are still valid. The ability to isolate the failure down to a single FBDIMM may
not be available on certain errors, and / or during early POST.
5.2.2.5 OS Watchdog Failure
If an operating system device driver is using the watchdog timer to detect software or hardware
failures and that timer expires, an asynchronous reset (ASR) is generated. This is equivalent to
a hard reset. The POST portion of the BIOS can query the BMC for watchdog reset events as
the system reboots, and logs this event in the SEL.
5.2.2.6 Boot Event
The BIOS downloads the system date and time to the BMC during POST and logs a boot event.
Software that parses the event log should not treat the boot event as an error.
5.2.3 Timestamp Clock Event
The BMC maintains a 4-byte internal timestamp clock used by the SEL and SDR subsystems.
The timestamp clock is incremented once per second.
5.2.3.1 No Real-time Clock (RTC) Access
After a BMC reset, the BMC sets the initial value of the timestamp clock to 0x00000000, after
which it is incremented once per second. A SEL event containing a timestamp from 0x00000000
to 0x14000000 has a timestamp value that is relative to BMC initialization.
During POST, the BIOS tells the BMC the current RTC time. The BMC maintains that time using
a hardware signal driven from the same oscillator that maintains the system’s time-of-day clock.
If the user changes the RTC during operation, SMS is responsible for synchronizing the time
with the BMC.
Note: The BMC can lose the current timestamp during a BMC cold reset or a firmware update.
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