Intel® 5000 Series Chipsets Server Board Family Datasheet System Management
Revision 1.1
Intel order number D38960-004
103
4.3 BMC Reset Control
The following table shows the sources of BMC resets, and the actions by the server and the
BMC as a result.
Table 34. BMC Reset Sources and Actions
Reset Source System Reset? BMC Reset
Standby power comes up No (system is not up yet) Yes
BMC exits firmware update mode No Yes
4.3.1 BMC Exits Firmware Update Mode
The BMC firmware can be updated using firmware transfer commands through the LPC
interface. The BMC automatically enters firmware transfer mode if it detects that the Force
Update signal is asserted during initialization, or if the operation code checksum validation fails.
Upon exit from firmware transfer mode, the BMC resets itself. The BMC will re-synchronize itself
to the state of the processor and power control signals it finds when it initializes.
4.4 System Initialization
4.4.1 Fault Resilient Booting (FRB)
Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support that,
under certain conditions, allows a multiprocessor system to boot even if the bootstrap processor
(BSP) fails. The intent of the FRB algorithms is to detect BSP failure, disable the failed
processor, and reset the server with a different processor as the BSP. For Intel
®
5000 platforms,
only FRB2 is supported using watchdog timer commands.
4.4.1.1 Processor Disabling
To disable a processor, the BMC asserts the corresponding Processor Disable signal in
conjunction with resetting the system. The signal used for this purpose is specific for the
processor type.
The BMC will enforce that at least one processor always remains enabled. On platforms that
use one of the Intel
®
5000 Series Chipsets, it is not expected that processors will be disabled
except for debug purposes.
4.4.1.2 BSP Identification
The BMC provides positive indication of which processor(s) have been disabled. It does not
indicate which processor is the BSP.
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