System BIOS Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
30
3.2.16 Intel
®
Virtualization Technology
Intel
®
Virtualization Technology is designed to support multiple software environments sharing
the same hardware resources. Each software environment may consist of operating system and
applications. The Intel
®
Virtualization Technology can be enabled or disabled in BIOS Setup.
The default behavior is disabled.
Note: If the Setup options are changed to enable or disable the Intel
®
Virtualization Technology
setting in the processor, the user must perform an AC power cycle before the changes will take
effect.
3.2.17 Acoustical Fan Speed Control
The processors implement a methodology for managing processor temperatures that supports
acoustic noise reduction through fan speed control. There are two components to the
temperature calculation used to regulate the fans: T
CONTROL offset and TCONTROL base. The
BIOS retrieves the T
CONTROL offset from a processor MSR and sends it to the BMC. The BMC
is responsible for getting the T
CONTROL base from the sensor data records and adding it to the
value received from the BIOS.
3.3 Memory
The Intel
®
5000 MCH supports fully-buffered DIMM (FBDIMM) technology. The integrated
Memory Controller Hub in the Intel
®
5000 MCH divides the FBDIMMs on the board into two
autonomous sets called branches. Each branch has two channels. In dual-channel mode,
FBDIMMs on adjacent channels work in lock-step to provide the same cache line data, and a
combined ECC. In the single-channel mode, only Channel 0 is active.
The BIOS is able to configure the memory controller dynamically in accordance with the
available FBDIMM population and the selected RAS (reliability, availability, serviceability) mode
of operation.
Note: Memory sparing and mirroring features are currently disabled and will be made available
after production launch.
3.3.1 Memory Sizing and Configuration
The BIOS supports various memory module sizes and configurations. These combinations of
sizes and configurations are valid only for FBDIMMs approved by Intel. The BIOS reads the
Serial Presence Detect (SPD) SEEPROMs on each installed memory module to determine the
size and timing characteristics of the installed memory modules (FBDIMMs). The memory-sizing
algorithm then determines the cumulative size of each row of FBDIMMs. The BIOS programs
the memory controller in the chipset accordingly, such that the range of memory accessible from
the processor is mapped into the correct FBDIMM or set of FBDIMMs.