Intel 5000 Series User Manual

Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture
Revision 1.1
Intel order number D38960-004
19
2.4.9.1 Ultra ATA/100
The IDE interface of the Intel
®
631xESB / 632xESB I/O Controller Hub ICH DMA protocol
redefines signals on the IDE cable to allow both host and target throttling of data and transfer
rates of up to 100 MB/s.
2.4.9.2 IDE Initialization
The BIOS supports the ATA/ATAPI Specification, version 6. The BIOS initializes the embedded
IDE controller in the chipset (Intel
®
631xESB / 632xESB I/O Controller Hub) and the IDE device
that is connected to this device. The BIOS scans the IDE device and programs the controller
and the device with their optimum timings. The IDE disk read/write services that are provided by
the BIOS use PIO mode, but the BIOS programs the necessary Ultra DMA registers in the IDE
controller so the operating system can use the Ultra DMA modes.
2.4.10 Serial ATA (SATA) Support
The integrated Serial ATA (SATA) controller of the Intel
®
631xESB / 632xESB I/O Controller
Hub provides up to six SATA or four SAS devices ports on the server board. The SATA ports
can be enabled / disabled and/or configured through the BIOS Setup Utility.
The BIOS initializes and supports SATA devices just like PATA devices. It initializes the
embedded IDE controllers in the chipset and any SATA devices that are connected to these
controllers. From a software standpoint, SATA controllers present the same register interface as
PATA controllers. Hot-plugging SATA drives during the boot process is not supported by the
BIOS and may result in undefined behavior.
The SATA function in the Intel
®
631xESB / 632xESB I/O Controller Hub has dual modes of
operation to support different operating system conditions. In the case of native IDE-enabled
operating systems, the Intel
®
631xESB / 632xESB I/O Controller Hub has separate PCI
functions for serial and parallel ATA. To support legacy operating systems, there is only one PCI
function for both the serial and parallel ATA ports.
The MAP register provides the ability to share PCI functions. When sharing is enabled, all I/O
decoding is done through the SATA registers. A software write to the Function Disable Register
(D31, F0, offset F2h, bit 1) causes Device 31, Function 1 (IDE controller) to be hidden and its
configuration registers are not used. The SATA Capability Pointer Register (offset 34h) will
change to indicate that Message Signaled Interrupt (MSI) is not supported in combined mode.
The Intel
®
631xESB / 632xESB I/O Controller Hub SATA controller features two sets of interface
signals that can be independently enabled or disabled. Each interface is supported by an
independent DMA controller. The Intel
®
631xESB / 632xESB I/O Controller Hub SATA controller
interacts with an attached mass storage device through a register interface that is equivalent to
that which is presented by a traditional IDE host adapter. The host software follows existing
standards and conventions when accessing the register interface and follows standard
command protocol conventions.
SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer
rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the
SATA device or the system BIOS.

Intel 5000 Series Specifications

General

Brand	Intel
Model	5000 Series
Category	Server Board
Language	English