Intel 5000 Series User Manual

Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS
Revision 1.1
Intel order number D38960-004
33
3.3.4.2 Host Frequency and Gear Ratio
The host frequency is the speed of the memory interface of the Intel
®
5000 Series Chipset. This
frequency determines the speed at which the chipset completes a memory transaction. The
gear ratio determines the relative speed between the processor interface and the memory
interface.
The BIOS supports two frequencies: 533 MHz and 667 MHz. The BIOS also provides an auto-
select feature that provides automatic selection and configuration of the host frequency and
gear ratio.
During memory discovery, the BIOS keeps track of the minimum latency requirements of each
installed FBDIMM by recording relevant latency requirements from each FBDIMM’s SPD data.
The BIOS then arrives at a common frequency that matches the requirements of all components
and then configures the memory system, as well as the FBDIMMs, for that common frequency.
3.3.5 Memory Test
3.3.5.1 Integrated Memory BIST Engine
The Intel
®
5000 MCH incorporates an integrated Memory Built-in Self Test (BIST) engine that is
enabled to provide extensive coverage of memory errors at both the memory cell level, as well
as the data paths emanating from the FBDIMMs.
The BIOS uses this in-built Memory BIST engine to perform two specific operations:
 ECC fill to set the memory contents to a known state. This provides a bare minimum
error detection capability, and is referred to as the Basic Memory Test algorithm.
 Extensive FBDIMM testing to search for memory errors on both the memory cells and
the data paths. This is referred to as the Comprehensive Memory Test algorithm.
The Memory BIST engine replaces the traditional BIOS-based software memory tests. The
Memory BIST engine is much faster than the traditional memory tests. The BIOS also uses the
Memory BIST to initialize memory at the end of the memory discovery process. The BIOS does
not execute Memory BIST when the system is waking from an S3 sleep mode (S3 Resume) for
systems that support S3.
3.3.6 Memory Scrub Engine
The Intel
®
5000 MCH incorporates a memory scrub engine. When this integrated component is
enabled, it performs periodic checks on the memory cells, and identifies and corrects single-bit
errors. Two types of scrubbing operations are possible:
 Demand scrubbing – executes when an error is encountered during a normal read/write
of data.
 Patrol scrubbing – proactively walks through populated memory space seeking soft
errors.
The BIOS enables both demand scrubbing and patrol scrubbing by default.

Intel 5000 Series Specifications

General

Brand	Intel
Model	5000 Series
Category	Server Board
Language	English