Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
4
2.1 Intel
®
5000 MCH Components
The chipsets consist of two components that together are responsible for providing the interface
between all major sub-systems found on the Intel
®
server or workstation board. These sub-
systems include the processor, memory, and I/O sub-systems. These components are:
Intel
®
5000 Memory Controller Hub (Intel
®
5000 MCH)
Intel
®
Enterprise South Bridge 2 (Intel® 631xESB / 632xESB I/O Controller Hub)
The following sub-sections provide an overview of the primary functions and supported features
of each chipset component used on the Intel
®
boards that utilize the Intel
®
5000 MCH. Later
sections in this chapter provide more detail on how each sub-system is implemented.
Note: See the Intel
®
server board or workstation board technical product specification that
applies to your product for feature-specific support information.
2.1.1 Memory Controller Hub (Intel
®
5000 MCH)
The Intel
®
5000 MCH is a 1432-ball FC-BGA package configured to support the following
interfaces:
CPU dual, independent system bus at 667-, 1066-, or 1333-MHz operation.
Four fully-buffered DIMM (FBD) channels supporting fully-buffered DDR2 DIMMs
(FBDIMMs), 24-lane serial bus at 6.4 GB/s (533 MT/s) and 8 GB/s (667 MT/s) peak
theoretical bandwidth per channel. This allows a total of 25.6 GB/s and 64.6 GB/s peak
theoretical bandwidth for all four Channels combined.
One PCI Express* x8 port with an aggregate bandwidth of 4 GB/s interface to the Intel®
631xESB / 632xESB I/O Controller Hub.
One PCI Express x8 port with an aggregate bandwidth of 4 GB/s interface to x8 PCI
Express Connector.
One PCI Express x8 port with an aggregate bandwidth of 4 GB/s interface to x8 PCI
Express Connector.
One PCI Express x4 ESI port with an aggregate bandwidth of 2 GB/s interface to the
Intel® 631xESB / 632xESB I/O Controller Hub.
2.1.1.1 System Bus
The Intel
®
5000 MCH supports either single- or dual-processor configurations using the Intel
®
Xeon
®
5000 Sequence processor with a 2x 2 MB cache. The Intel
®
5000 MCH supports a base
system bus frequency of 266 MHz and 333 MHz for Intel
®
5000 Series Chipsets. The address
and request interface is double-pumped to 533 MHz, and the 64-bit data interface (+ parity) is
quad-pumped to 1066 MHz. This provides a matched system bus address and data bandwidths
of 8.5 GB/s.
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