Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS
Revision 1.1
Intel order number D38960-004
25
The BIOS ID is used to identify the BIOS image. It is not used to designate either the board ID
or the BIOS phase. The board ID is available in the SMBIOS type 2 structure in which the phase
of the BIOS can be determined by the release notes associated with the image. The board ID is
also available in BIOS Setup.
3.2 Processors
3.2.1 CPUID
The following processors are supported on Intel
®
server boards and systems that use the Intel
®
5000 Series Chipset, with their respective CPU ID:
Dual-Core Intel
®
Xeon
®
Processor 5000 sequence: CPU ID – 00000F6xh
Dual-Core Intel
®
Xeon
®
Processor 5000 sequence low voltage: CPU ID – 000006Fxh
Table 3. Supported Processor Configurations
Processor Family System Bus Speed Core Frequency Cache Watts Support
Intel
®
Xeon
®
Processor 533 MHz All No
Intel
®
Xeon
®
Processor 800 MHz All No
Intel
®
Xeon
®
Processor 5050 667 MHz 3.0 GHz 2x 2 MB 95 Yes
Intel
®
Xeon
®
Processor 5060 1066 MHz 3.2 GHz 2x 2 MB 130 Yes
Intel
®
Xeon
®
Processor 5063 1066 MHz 3.2 GHz 2x 2 MB 95 Yes
Intel
®
Xeon
®
Processor 5080 1066 MHz 3.73 GHz 2x 2 MB 130 Yes
Intel
®
Xeon
®
Processor 51xx 1333/1066 MHz TBD TBD TBD Yes
3.2.2 Multiple Processor Initialization
IA-32 processors have a microcode-based bootstrap processor (BSP) arbitration protocol. A
processor that does not perform the role of BSP is referred to as an application processor (AP).
The Intel
®
5000 Series Chipset memory controller hub (MCH) has two processor system buses,
each of which accommodates a single Dual-Core Intel
®
Xeon
®
processor 5000 sequence. At
reset, the hardware arbitration chooses one BSP from the available processor cores per system
bus. However, the BIOS power-on self-test (POST) code requires only one processor for
execution. This requires the BIOS to elect a system BSP using registers in the Intel
®
5000 MCH.
The BIOS cannot guarantee which processor will be the system BSP, only that a system BSP
will be selected. In the remainder of this document, the system BSP is referred to as the BSP.
The BSP is responsible for executing the BIOS POST and preparing the server to boot the
operating system. At boot time, the server is in virtual wire mode and the BSP alone is
programmed to accept local interrupts (INTR driven by programmable interrupt controller (PIC)
and non-maskable interrupt (NMI)).
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