Intel 5000 Series User Manual

Intel® 5000 Series Chipsets Server Board Family Datasheet Functional Architecture
Revision 1.1
Intel order number D38960-004
5
2.1.1.2 Intel
®
5000 MCH Memory Sub-System Overview
The Intel
®
5000 MCH provides an integrated memory controller for direct connection to four
channels of registered fully-buffered DIMM (FBD) DDR2 533/667 MHz memory (stacked or
unstacked). Peak theoretical memory data bandwidth using FBD 533/667 MHz technology is 6.4
and 8 GB/s, respectively.
When all four memory channels are populated and operating, they function in lock-step mode.
The maximum supported FBD DDR2 533/667 MHz memory configuration is 64 GB.
The Intel
®
5000 MCH memory interface provides several reliability, availability, serviceability,
usability, and manageability (RASUM) features, including:
 Memory mirroring allows two copies of all data in the memory subsystem (one on each
channel) to be maintained.
 Memory sparing allows one DIMM per channel to be held in reserve and brought on-line
if another FBDIMM in the channel becomes defective.
 Hardware periodic memory scrubbing, including demand scrub support.
 Retry on uncorrectable memory errors.
 Intel
®
x4/x8 Single Device Data Correction (SDDC) for memory error detection and
correction of any number of bit failures in a single x4/x8 memory device.
Note: Memory sparing and memory mirroring are mutually exclusive.
Note: Memory sparing and mirroring features are currently disabled and will be made available
after production launch.
2.1.1.3 PCI Express* Interface
The Intel
®
5000 MCH supports the PCI Express* high-speed serial I/O interface for superior I/O
bandwidth. The scalable PCI Express interface of the Intel
®
5000 MCH complies with the PCI
Express Interface Specification, Revision 1.0a.
The Intel
®
5000 MCH provides three x8 PCI Express* interfaces, each with a maximum
theoretical bandwidth of 4.2 GB/s. Each of these x8 PCI Express interfaces may alternatively be
configured as two independent x4 PCI Express interfaces. A PCI Express interface/port is
defined as a collection of lanes. Each lane (x1) consists of two striped differential pairs in each
direction (transmit and receive). The raw bit-rate on the data pins of 2.5 Gb/s, results in a real
bandwidth of 250 MB/s per pair, given the 8/10 bit encoding used to transmit data across this
interface.
The Intel
®
5000 MCH is a root-class component as defined in the PCI Express Interface
Specification. The PCI Express* interfaces of the Intel
®
5000 MCH support connections to a
variety of bridges and devices that are compliant with the same revision of the specification.

Intel 5000 Series Specifications

General

Brand	Intel
Model	5000 Series
Category	Server Board
Language	English