Functional Architecture Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
6
2.1.1.3.1 PCI Express* Training
To establish a connection between PCI Express* endpoints, the endpoints participate in a
sequence of steps called training. This sequence establishes the operational width of the link
and adjusts skews of the various lanes within a link so that the data sample points can correctly
take a data sample from the link.
In the case of a x8 port, the x4 link-pairs first attempt to train independently, and will collapse to
a single link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they negotiate to train at the highest
common width, and step down in its supported link widths to succeed in training. The result may
be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or a x4 link, it allows
communication between the two devices. Software can then interrogate the device at the other
end of the link to determine why it failed to train at a higher width. This would not be possible
without support for the x1 link width.
Width negotiation is done only during training or retraining, not during recovery.
2.1.1.3.2 PCI Express* Retry
The PCI Express* interface incorporates a link-level retry mechanism. The hardware detects a
corrupted transmission packet and performs a retry of that packet and all following packets.
Although this causes a temporary interruption in the delivery of packets, the retry helps to
maintain the link integrity.
2.1.1.3.3 PCI Express* Link Recovery
If excessive errors occur, the hardware can determine that the quality of the connection is in
question and the end points can enter a quick training sequence, known as recovery. The width
of the connection will not be renegotiated, but the adjustment of skew between lanes of the link
might occur. This occurs without any software intervention, but the software might be notified.
2.1.1.3.4 PCI Express* Data Protection
The PCI Express* high-speed serial interface uses traditional CRC protection. The data packets
use a 32-bit CRC protection scheme, the same CRC-32 used by Ethernet. The smaller link
packets use a 16-bit CRC scheme. Since packets utilize 8B/10B encoding, and not all
encodings are used; this provides further data protection, as illegal codes can be detected. If
errors are detected on the reception of data packets due to various transients, these data
packets can be retransmitted. Hardware logic supports this link-level retry without software
intervention.
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