System Management Intel® 5000 Series Chipsets Server Board Family Datasheet
Revision 1.1
Intel order number D38960-004
104
4.4.1.3 Watchdog Timer Timeout Reason Bits
To implement FRB2, during POST the BIOS determines whether a BMC watchdog timer
timeout occurred on the previous boot attempt. If it finds a watchdog timeout did occur, it
determines whether that timeout was an FRB2 timeout, system management software (SMS)
timeout, or an intentional, timed hard reset.
4.4.1.4 FRB2
FRB2 refers to the FRB algorithm that provides for detection of system failures, such as hangs,
during POST. The BIOS uses the BMC watchdog timer to back up its operation during POST.
The BIOS configures the watchdog timer to indicate that the BIOS is using the timer for the
FRB2 phase of the boot operation.
After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and
loads the watchdog timer with the new timeout interval.
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if so
configured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes.
The BMC then hard resets the system, assuming the BIOS selected reset as the watchdog
timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan
and before displaying a request for a boot password. If the processor fails and causes an FRB2
time-out, the BMC resets the system.
As part of its normal operation, BIOS obtains the watchdog expiration status from the BMC. If
this status shows expiration with an FRB2 timer, the BIOS creates an entry in the system event
log (SEL) which indicates an FRB2 failure. It includes the last POST code generated during the
previous boot attempt in the OEM bytes of the event entry. FRB2 failure is not reflected in the
processor status sensor value.
Although an FRB2 failure will cause events to be logged into the SEL, there is no effect on the
front panel LEDs.
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