Tutorial 7
Keysight 34970A/34972A User’s Guide 289
For the lower voltage ranges, the internal DMM’s input resistance is essentially
that of the input amplifier. The input amplifier uses a low-bias current (less than
50 pA) FET input stage yielding an input resistance greater than 10 GΩ. On the
100V and 300V input ranges, the input resistance is determined by the total
resistance of the 100:1 divider. You can also set the input resistance to 10 MΩ by
continuously closing the High V switch (for more information on DC input
resistance, see page 142).
Sources of Error in DC Voltage Measurements
Common Mode Rejection
Ideally, the internal DMM is completely isolated from earth-referenced circuits.
However, there is finite resistance and capacitance between the input LO terminal
and earth ground. If the input terminals are both driven by an earth-referenced
signal (V
f
) then a current will flow through R
S
and create a voltage drop V
L
as
shown below.
Any resulting voltage (V
L
) will appear as an input to the internal DMM. As the
value of R
S
approaches zero, so does the error. Additionally, if V
f
is at the power
line frequency (50 Hz or 60 Hz), the noise can be greatly reduced by setting the
internal DMM’s integration time to 1 PLC
or greater (see page 133 for a discussion of integration time).
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