NXP Semiconductors MPC5777M - Page 110

MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors110
Figure 40. MII receive signal timing diagram
3.16.3.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the MPC5777M Microcontroller Reference Manual’s Fast Ethernet Controller (FEC) chapter for details of this option
and how to enable it.
Table 59. MII transmit signal timing
1
1
All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.
Symbol Characteristic
Value
2
2
Output parameters are valid for C
L
= 25 pF, where C
L
is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
Unit
Min Max
M5 CC TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns
M6 CC TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
M7 CC TX_CLK pulse width high 35% 65% TX_CLK period
M8 CC TX_CLK pulse width low 35% 65% TX_CLK period
M1
M2
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M3
M4