NXP Semiconductors MPC5777M - Page 111

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 111
Figure 41. MII transmit signal timing diagram
3.16.3.3 MII async inputs signal timing (CRS and COL)
Figure 42. MII async inputs timing diagram
3.16.3.4 MII and RMII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 60. MII async inputs signal timing
Symbol Characteristic
Value
Unit
Min Max
M9 CC CRS, COL minimum pulse width 1.5 — TX_CLK period
Table 61. MII serial management channel timing
1
1
All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and
2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
Symbol Characteristic
Value
2
Unit
Min Max
M10 CC MDC falling edge to MDIO output invalid (minimum
propagation delay)
0— ns
M11 CC MDC falling edge to MDIO output valid (max prop
delay)
—25 ns
M12 CC MDIO (input) to MDC rising edge setup 10 — ns
M13 CC MDIO (input) to MDC rising edge hold 0 — ns
M14 CC MDC pulse width high 40% 60% MDC period
M15 CC MDC pulse width low 40% 60% MDC period
M6
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M7
M8
CRS, COL
M9