MPC5777M Microcontroller Data Sheet, Rev. 6
Electrical characteristics
NXP Semiconductors112
Figure 43. MII serial management channel timing diagram
3.16.3.5 RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of
the REF_CLK frequency.
2
Output parameters are valid for C
L
= 25 pF, where C
L
is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
Table 62. RMII receive signal timing
1
1
All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
Symbol Characteristic
Value
Unit
Min Max
R1 CC RXD[1:0], CRS_DV to REF_CLK setup 4 — ns
R2 CC REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 CC REF_CLK pulse width high 35% 65% REF_CLK period
R4 CC REF_CLK pulse width low 35% 65% REF_CLK period
M11
MDC (output)
MDIO (output)
M12
M13
MDIO (input)
M10
M14
M15
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