NXP Semiconductors MPC5777M - Page 113

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 113
Figure 44. RMII receive signal timing diagram
3.16.3.6 RMII transmit signal timing (TXD[1:0], TX_EN)
The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of
the REF_CLK frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK,
and the timing is the same in either case. These options allows the use of non-compliant RMII PHYs.
Figure 45. RMII transmit signal timing diagram
Table 63. RMII transmit signal timing
1, 2
1
RMII timing is valid only up to a maximum of 150
o
C junction temperature.
2
All timing specifications are referenced for TTL or CMOS input levels for REF_CLK to the valid output levels, 0.8 V
and 2.0 V.
Symbol Characteristic
Value
3
3
Output parameters are valid for C
L
= 25 pF, where C
L
is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
Unit
Min Max
R5 CC REF_CLK to TXD[1:0], TX_EN invalid 2 — ns
R6 CC REF_CLK to TXD[1:0], TX_EN valid — 16 ns
R7 CC REF_CLK pulse width high 35% 65% REF_CLK period
R8 CC REF_CLK pulse width low 35% 65% REF_CLK period
R1
R2
REF_CLK (input)
RXD[1:0] (inputs)
CRS_DV
R3
R4
R6
REF_CLK (input)
TXD[1:0] (outputs)
TX_EN
R5
R7
R8