NXP Semiconductors MPC5777M - Page 25

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 25
5
Although the maximum V
DD_LV
operating voltage is 1.38 V, reset is not entered at that voltage. An external voltage monitor
is needed or the HVD140_C can be monitored (via an interrupt or by polling the HVD140_C flag bit). Performance above
1.38 V is not guaranteed, and allowed operation above 1.38 V is defined in Absolute maximum ratings.
6
In the LVD/HVD disabled case, it is necessary for the system to be within a higher voltage range during destructive reset
events.
7
Maximum core voltage is not permitted for entire product life. See Absolute maximum rating.
8
When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.
9
Vdd_lv should be above 1.24 V during destructive resets or POR events.
10
VDD_HV_IO_MAIN range limited to 4.75–5.25 V when FERS = 1 to enable the fast erase time of the flash memory.
11
During power up operation, the minimum required voltage to come out of reset state is determined by the V
PORUP_HV
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
PORUP_HV
monitor is connected
to the V
DD_HV_IO_MAIN0
physical I/O segment.
12
When the LVD/HVDs are enabled, the V
DD_HV_IO_MAIN
must be less than 5.412 V to exit from a destructive reset.
13
Maximum voltage is not permitted for entire product life. See Absolute maximum rating.
14
When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor
externally supply voltage may result in erroneous operation of the device.
15
When these LVD/HVDs are disabled, the V
DD_HV_IO_MAIN
supply must be between 3.182 V and 5.412 V.
16
Reduced output capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics.
17
When the LVD/HVDs are disabled, the VDD_HV_IO_MAIN must be between 3.024 V and 5.412 V.
18
The PMC supply voltage (V
DD_HV_PMC
) must be within the correct range (see the V
DD_HV_PMC
specification).
19
When the LVD/HVDs are disabled, the HV I/O JTAG supply (V
DD_HV_IO_JTAG
) must be above 3.024 V.
20
When the LVD/HVDs are disabled, the HV OSC supply (V
DD_HV_OSC
) must be above 3.024 V.
21
Flash read operation is supported for a minimum V
DD_HV_PMC
value of 3.15 V. Flash read, program, and erase operations
are supported for a minimum V
DD_HV_PMC
value of 3.5 V.
22
When the LVD/HVDs are disabled, the V
DD_HV_PMC
must be below 5.412 V during destructive reset events.
23
A minimum of 4.5 V is required to guarantee correct user logic BIST operation.
24
During power up operation, the minimum required voltage to come out of reset state is determined by the V
PORUP_HV
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
PORUP_HV
monitor is connected
to the V
DD_HV_IO_MAIN0
physical I/O segment.
25
Above Ta = 25°C, the minimum V
DD_HV_PMC
voltage is 3.6 V.
26
With the reduced internal regulator output capability, erases and writes to the device flash cannot be guaranteed for a single
event and multiple erases and writes may be necessary. User logic BIST is not supported with reduced capability.
27
RAM data retention is guaranteed at a voltage that is always below the maximum brownout flag trip point voltage (see the
DC Electrical Specification table). The minimum V
DDSTBY
voltage at the pin is larger in order to account for on-chip IR drop
and noise. There is no effect on RAM operation when V
DDSTBY
is below 1.1 V, and V
DD_LV
is above the minimum operating
value.
28
Non-regulated supplies can be used on the VDDSTBY pin if the absolute maximum and operating condition voltage limits
are met. There is no static clamp to a supply rail for the VDDSTBY pin, only dynamic protection for ESD events.
29
The VDDSTBY pin should be connected to ground in the application when the standby RAM feature is not used.
30
V
DD_HV_ADV_S
is required to be between 4.5 V and 5.5 V to read the internal Temperature Sensor and Bandgap Reference.
31
SAR ADC only. SDADC minimum is 4.5 V.
32
The ADC is functional up to 5.9V with no reliability issues, but performance is not guaranteed.
33
When the LVD/HVDs are disabled, the HV ADC supply (V
DD_HV_ADV
) must be above 3.182 V.
34
For supply voltages between 3.0 V and 4.0 V there is no guaranteed precision of ADC (accuracy/linearity). ADCs recover to
a fully functional state when the voltage rises above 4.0 V.
35
V
DD_HV_ADR_S
must be between 4.5 V and 5.5 V for accurate reading of the device Temperature Sensor.
36
Full device lifetime without performance degradation
37
I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the
Absolute maximum ratings table for maximum input current for reliability requirements.