NXP Semiconductors MPC5777M - Page 69

Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 69
t
SM2NM_TX
CC Transmitter startup time (sleep mode
to normal mode)
7
Not applicable to the
MSC/DSPI LVDS pad
—0.20.5µs
t
PD2NM_RX
CC Receiver startup time (power down
to normal mode)
8
— — 20 40 ns
t
PD2SM_RX
CC Receiver startup time (power down
to sleep mode)
9
Not applicable to the
MSC/DSPI LVDS pad
—2050ns
I
LVDS_BIAS
CC LVDS bias current consumption Tx or Rx enabled — — 0.95 mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z
0
SR Transmission line characteristic
impedance
— 47.55052.5
Z
DIFF
SR Transmission line differential
impedance
— 95 100 105 
RECEIVER
V
ICOM
SR Common mode voltage — 0.15
10
—1.6
11
V
|
VI
| SR Differential input voltage
12
— 100 — — mV
V
HYS
CC Input hysteresis — 25 — — mV
R
IN
CC Terminating resistance 3.0 V–5.5 V 80 125 150 
C
IN
CC Differential input capacitance
13
— — 3.5 6.0 pF
I
LVDS_RX
CC Receiver DC current consumption Enabled — — 0.5 mA
1
The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed De-
bug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.
2
All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3
All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in
the LVDS control registers (LCR) of the LFAST and High-Speed Debug modules. The value of the LCR bits for the
LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode.
Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS
in the corresponding SIUL2 MSCR ODC field.
4
Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmit-
ter electrical characteristic tables.
5
Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after
being enabled.
6
Total transmitter startup time from power down to normal mode is t
STRT_BIAS
+ t
PD2NM_TX
+ 2 peripheral bridge clock
periods.
7
Total transmitter startup time from sleep mode to normal mode is t
SM2NM_TX
+ 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
8
Total receiver startup time from power down to normal mode is t
STRT_BIAS
+ t
PD2NM_RX
+ 2 peripheral bridge clock
periods.
9
Total receiver startup time from power down to sleep mode is t
PD2SM_RX
+ 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
10
Absolute min = 0.15 V – (285 mV/2) = 0 V
11
Absolute max = 1.6 V + (285 mV/2) = 1.743 V
Table 30. LVDS pad startup and receiver electrical characteristics
1,2
(continued)
Symbol Parameter Conditions
Value
Unit
Min Typ Max