NXP Semiconductors QorIQ LS1043ARDB - Page 13

Watchpoint
Cross
Trigger
Trust Zone
Power Management
IFC, QuadSPI, SPI
2x DUART
32-bit
DDR3L/4
Memory Controller
Real Time Debug
Perf
Monitor
4x I2C, 4x GPIO
Secure Boot
8x FlexTimer
Queue
Manager
Buffer
Manager
Parse, classify,
distribute
1/2.5/10G
PCI Express 2.0
SATA 3.0
Trace
4-Lane, 10 GHz SerDes
ARM Cortex-
A53 64b Cores
1G
SMMUs
3x USB3.0 w/PHY
CCI-400™ Coherency Fabric
32 KB
D-Cache
32 KB
I-Cache
ARM Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
ARM Cortex-
A53 64b Cores
32 KB
D-Cache
32 KB
I-Cache
ARM Cortex-
A53 64b Cores
1G
1G
1G
1/2.5G
1G
QUICC Engine
PCI Express 2.0
PCI Express 2.0
Frame Manager
SD/SDIO/eMMC
DMA
6x LPUART
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Security
Engine
(SEC)
DPAA Hardware
Arm
®
Cortex
®
-A53
64-bit Core
32 KB
D-Cache
32 KB
I-Cache
1 MB L2 - Cache
Figure 1-1. LS1043A processor block diagram
The figure below shows the LS1043ARDB block diagram.
Chapter 1 Introduction
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
NXP Semiconductors 13