NXP Semiconductors QorIQ LS1043ARDB - Page 68

Revision
number
Date Topic cross-reference Change description
GPIOs Updated the section
CPLD Programming • Updated the reset value of the
CPLD_VER_SUB register
• Updated details of bit 7 of the
CPLD_SOFT_MUX_ON register
• Added a new register,
CPLD_EVDD_SEL
Rev. 1 11/2015 Introduction Changed the LS1043ARDB part number from
LS1043ARDB-PA to LS1043ARDB-PB
Board features Changed core clock frequency from 1.5 GHz to
1.6 GHz in Table 1-3
CPLD memory map / register
definitions
• Changed the reset value of the
CPLD_VER_SUB register to 04h
• Changed the reset value of the
CPLD_PCBA_VER register to 03h
Rev. 0 08/2015 Initial public release
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 4, 11/2017
68 NXP Semiconductors