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CS/CJ/NSJ Series Instructions Reference Manual (W474)
4. Instruction Execution Times and Number of Steps
4-1 CJ2 CPU Unit Instruction Execution Times and Number of Steps
4
4-1-32 Text String Processing Instructions
4-1-32 Text String Processing Instructions
CONDITIONAL BLOCK EXIT EXIT (bit
address)
2 9.8 14.8 Block exited (bit ON)
3.6 4.2 Block not exited (bit
OFF)
CONDITIONAL BLOCK EXIT
(NOT)
EXIT NOT (bit
address)
2 3.6 4.3 Block exited (bit
OFF)
8.9 14.9 Block not exited (bit
ON)
Branching IF (execution
condition)
1 1.9 2.4 IF true (input condi-
tion ON)
3.8 6.4 IF false (input condi-
tion OFF)
IF (bit address) 2 3.2 4.0 IF true (bit ON)
5.1 8.0 IF false (bit OFF)
Branching (NOT) IF NOT (bit
address)
2 5.1 8.2 IF true (bit OFF)
3.2 4.1 IF false (bit ON)
Branching ELSE 1 3.5 5.7 IF true
5.3 7.3 IF false
Branching IEND 1 5.3 8.5 IF true
2.0 2.4 IF false
ONE CYCLE AND WAIT WAIT (execu-
tion condition)
1 10.0 15.9 Do not wait (input
condition ON)
1.4 1.9 Wait (input condi-
tion OFF)
WAIT (bit
address)
2 9.2 13.5 Do not wait (bit ON)
2.6 3.7 Wait (bit OFF)
ONE CYCLE AND WAIT
(NOT)
WAIT NOT (bit
address)
2 9.2 13.5 Do not wait (bit
OFF)
2.8 3.7 Wait (bit ON)
HUNDRED-MS TIMER WAIT TIMW 3 15.6 22.9 Default setting
16.0 23.2 Normal execution
TIMWX 3 15.1 21.7 Default setting
16.0 23.2 Normal execution
TEN-MS TIMER WAIT TMHW 3 15.7 22.6 Default setting
17.5 24.9 Normal execution
TMHWX 3 15.2 22.1 Default setting
16.4 23.4 Normal execution
COUNTER WAIT CNTW 4 13.7 20.5 Default setting
13.4 19.8 Normal execution
CNTWX 4 13.1 19.5 Default setting
13.5 19.7 Normal execution
Loop Control LOOP 1 4.6 9.1 ---
Loop Control LEND (execu-
tion condition)
1 4.2 8.6 Do not loop (input
condition ON)
3.9 6.5 Loop (input condi-
tion OFF)
LEND (bit
address)
2 6.7 10.4 Do not loop (bit ON)
6.6 8.2 Loop (bit OFF)
Loop Control (NOT) LEND NOT (bit
address)
2 6.7 10.9 Do not loop (bit
OFF)
6.6 8.2 Loop (bit ON)
Instruction Mnemonic Length
(steps)
ON execution time (µs) Conditions
CJ2H
CPU6@(-EIP)
CJ2M CPU@@
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