92
Sequence Input Instructions Section 3-2
Operand Specifications
Description LD NOT is used for the first normally closed bit from the bus bar, or for the first
normally closed bit of a logic block. If there is no immediate refreshing specifi-
cation, the specified bit in I/O memory is read and reversed. If there is an
immediate refreshing specification, the status of the Basic Input Unit’s input
terminal is read, reversed, and used.
LD NOT is used in the following circumstances as an instruction for indicating
a logical start.
• When directly connecting to the bus bar.
• When logic blocks are connected by AND LD or OR LD. (Used at the
beginning of a logic block.)
The AND LOAD and OR LOAD instructions are used to connect in series or in
parallel logic blocks beginning with LD or LD NOT.
At least one LOAD or LOAD NOT instruction is required for the execution con-
dition when output-related instructions cannot be connected directly to the
bus bar. If there is no LOAD or LOAD NOT instruction, a program error will
occur with the program check by the CX-Programmer.
When logic blocks are connected by AND LOAD or OR LOAD instructions, the
total number of AND LOAD/OR LOAD instructions must match the total num-
ber of LOAD/LOAD NOT instructions minus1. If they do not match, a program-
ming error will occur.
Flags There are no flags affected by this instruction.
Precautions Immediate refreshing (!) can be specified for LD NOT. An immediate refresh
instruction updates the status of the input bit for a CPU Unit built-in input just
before the instruction is executed.
Area LD NOT bit operand
CIO Area CIO 0.00 to CIO 6143.15
Work Area W0.00 to W511.15
Holding Bit Area H0.00 to H511.15
Auxiliary Bit Area A0.00 to A959.15
Timer Area T0000 to T4095
Counter Area C0000 to C4095
Task Flag Area TK00 to TK31
Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
Indirect DM addresses
in binary
---
Indirect DM addresses
in BCD
---
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
To Next Page
Loading...
