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Sequence Input Instructions Section 3-2
Description OR is used for a normally open bit connected in parallel. A normally open bit
is configured to form a logical OR with a logic block beginning with a LOAD or
LOAD NOT instruction (connected to the bus bar or at the beginning of the
logic block). If there is no immediate refreshing specification, the specified bit
in I/O memory is read. If there is an immediate refreshing specification, the
status of the CPU Unit’s input terminal is read.
Flags There are no flags affected by this instruction.
Precautions Differentiate up (@) or differentiate down (%) can be specified for OR. If differ-
entiate up (@) is specified, the execution condition is turned ON for one cycle
only after the status of the operand bit goes from OFF to ON. If differentiate
down (%) is specified, the execution condition is turned ON for one cycle only
after the status of the operand bit goes from ON to OFF.
Immediate refreshing (!) can be specified for OR. An immediate refresh
instruction updates the status of the input bit for a CPU Unit built-in input just
before the instruction is executed.
For OR, it is possible to combine immediate refreshing and up or down differ-
entiation (!@ or !%). If either of these is specified, the input is refreshed from
the CPU Unit just before the instruction is executed and the execution condi-
tion is turned ON for one cycle only after the status of the operand bit goes
from OFF to ON, or from ON to OFF.
Example
3-2-6 OR NOT: OR NOT
Purpose Reverses the status of the specified bit and takes a logical OR with the current
execution condition.
Ladder Symbol
Instruction Operand
LD 0.00
AND 0.01
AND 0.02
OR 0.03
AND 0.04
LD 0.05
AND 0.06
OR NOT 0.07
AND LD ---
OUT 100.00
100.00
0.060.05
0.07
0.040.020.010.00
0.03
Bus bar
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