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Sequence Input Instructions Section 3-2
Description AND NOT is used for a normally closed bit connected in series. AND NOT
cannot be directly connected to the bus bar, and cannot be used at the begin-
ning of a logic block. If there is no immediate refreshing specification, the
specified bit in I/O memory is read. If there is an immediate refreshing specifi-
cation, the status the CPU Unit’s input terminals is read.
Flags There are no flags affected by this instruction.
Precautions Immediate refreshing (!) can be specified for AND NOT. An immediate refresh
instruction updates the status of the input bit for CPU Unit built-in inputs just
before the instruction is executed.
Example
Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
TR Area ---
DM Area ---
Indirect DM addresses
in binary
---
Indirect DM addresses
in BCD
---
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Area AND NOT bit operand
Instruction Operand
LD 0.00
AND 0.01
LD 0.02
AND 0.03
LD 0.04
AND NOT 0.05
OR LD ---
AND LD ---
OUT 100.00
100.00
0.00 0.01 0.02 0.03
0.04 0.05
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