Omron CP - PROGRAMMING MANUAL 05-2007 - Page 148

115
Sequence Output Instructions Section 3-3
Operand Specifications
Description If there is no immediate refreshing specification, the status of the execution
condition (power flow) is reversed and written to a specified bit in I/O memory.
If there is an immediate refreshing specification, the status of the execution
condition (power flow) is reversed and also written to the CPU Unit’s output
terminal in addition to the output bit in I/O memory.
Flags There are no flags affected by this instruction.
Example
3-3-3 KEEP: KEEP(011)
Purpose Operates as a latching relay.
Ladder Symbol
Area OUT bit operand
CIO Area CIO 0.00 to CIO 6143.15
Work Area W0.00 to W511.15
Holding Bit Area H0.00 to H511.15
Auxiliary Bit Area A448.00 to A959.15
Timer Area ---
Counter Area ---
TR Area TR0 to TR15
DM Area ---
Indirect DM addresses in
binary
---
Indirect DM addresses in
BCD
---
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing using
Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to ,IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
Instruction Operand
LD 0.00
OUT 0.01
OUT NOT 0.02
0.00
100.00
100.01
KEEP(011)
B
S (Set)
R
(
Reset
)
B: Bit