532
Double-precision Floating-point Instructions Section 3-15
3-15-2 DOUBLE FLOATING TO 32-BIT: FIXLD(842)
Purpose Converts a double-precision (64-bit) floating-point value to 32-bit signed
binary data and places the result in the specified result words.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Description FIXLD(842) converts the integer portion of the double-precision (64-bit) float-
ing-point number in words S to S+3 (IEEE754-format) to 32-bit signed binary
data and places the result in D+1 and D.
Only the integer portion of the floating-point data is converted, and the fraction
portion is truncated. (The integer portion of the floating-point data must be
within the range of –2,147,483,648 to 2,147,483,647.)
FIXDL(842)
S
D
S: First source word
D: First destination word
Variations Executed Each Cycle for ON Condition FIXLD(842)
Executed Once for Upward Differentiation @FIXLD(842)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Area S D
CIO Area CIO 0 to CIO 6140 CIO 0 to CIO 6142
Work Area W0 to W508 W0 to W510
Holding Bit Area H0 to H508 H0 to H510
Auxiliary Bit Area A0 to A956 A448 to A958
Timer Area T0000 to T4092 T0000 to T4094
Counter Area C0000 to C4092 C0000 to C4094
DM Area D0 to D32764 D0 to D32766
Indirect DM addresses
in binary
@ D0 to @ D32767
Indirect DM addresses
in BCD
*D0 to *D32767
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
S+3
D+1
S
D
S+2 S+1
Floating-point data (64 bits)
Signed binary data (32 bits)
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