562
Double-precision Floating-point Instructions Section 3-15
Precautions The source data in words S to S+3 must be in IEEE754 floating-point data for-
mat.
3-15-20 DOUBLE EXPONENTIAL POWER: PWRD(860)
Purpose Raises a double-precision (64-bit) floating-point number to the power of
another double-precision (64-bit) floating-point number.
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Underflow Flag UF Unchanged
Negative Flag N ON if the result is negative.
OFF in all other cases.
Name Label Operation
PWRD(860)
B
E
D
B: First base word
E: First exponent word
D: First destination word
Variations Executed Each Cycle for ON Condition PWRD(860)
Executed Once for Upward Differentiation @PWRD(860)
Executed Once for Downward Differentiation Not supported.
Immediate Refreshing Specification Not supported.
Block program areas Step program areas Subroutines Interrupt tasks
OK OK OK OK
Area B E D
CIO Area CIO 0 to CIO 6140
Work Area W0 to W508
Holding Bit Area H0 to H508
Auxiliary Bit Area A0 to A956 A448 to A956
Timer Area T0000 to T4092
Counter Area C0000 to C4092
DM Area D0 to D32764
Indirect DM addresses
in binary
@ D0 to @ D32767
Indirect DM addresses
in BCD
*D0 to *D32767
Constants ---
Data Registers ---
Index Registers ---
Indirect addressing
using Index Registers
,IR0 to ,IR15
–2048 to +2047 ,IR0 to –2048 to +2047 ,IR15
DR0 to DR15, IR0 to IR15
,IR0+(++) to ,IR15+(++)
,–(– –)IR0 to, –(– –)IR15
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