RoentDek DLD40 - Figure 4.2: Pci2 Pcie Adapter Crate with; The HM1; HM1-B

Figure 4.2: PCI2PCIe adapter crate with PCIe card for the PC. Here two TDC8HP and a clock card are inserted
The PCI2PCIe adapter requires a mains cord with IEC-60320-C7 norm (only the EURO version of this cord can be supplied
by
RoentDek.
4.1.2
The HM1 / HM1-B
The HM1 is based on the GP1-chip of ACAM. It has a common-start input and 4 channels of stop inputs, all differential ECL.
The resolution is 133ps or better (adjustable) the range is 14bit or up to 30bit in a special long-range mode (resolution and
pulse-pair separation ability reduced). It can be operated in three modes:
a) In the standard mode, “transparent mode”, it can detect up to 3 or 4 hits per channel with a pulse pair resolution of about
15ns. The data acquisition (DAq) in this operation mode is managed by the PC. The DAq speed is limited to about 18kHz,
divided by the number of hits to be detected per channel. The data are stored in list-mode on the PC- hard disc. Two HM1
modules can be combined to a double module featuring effectively an 8-channel version (with half read-out speed), e.g. for
coincident read-out two DLD detectors (ISA version only).
b) The burst mode is a pre-calculated transparent mode (only available in the HM1-B module). The values for x1,x2,y1 and y2
are calculated inside the HM1-B Module to x, y and z. x, y and z is then coded into a single 32bit value. The number of bit
for x, y and z can be programmed. This 32bit value is store in a small FIFO. Only 1 hit can be detected in this mode. This
mode is mostly controlled by the HM1-B itself, therefore the DAq speed is about 150kHz.
c) In the so called histogram mode (optional, not for HM1/T) the DAq speed is significantly enhanced (more than 1MHz). The
data (only single hits per channel are registered) are stored on the TDC board in a 2D histogram (X and Y position, 11bit)
or 3D histogram (X, Y and Z=TOF) memory. After a measuring cycle the content of the histogram can be transferred to
the PC in a block for further data treatment. A dual memory bank on the board allows continuous data taking even during
data transfer to the PC. The range of the TDC is limited by the histogram partitioning.
The HM1-B is fully compatible to the HM1 as well as the HM1/T model. Additionally to the HM1 this module has the burst
mode ability.
Page 54 of 83 MCP Delay Line Detector Manual (11.0.1304.1)