FIGURE 2.6: RESPONSE OF A DELAY-LINE TO A SIGNAL PASSING THROUGH A FT12TP(HEX) PLUG. UPPER TRACE: INPUT
SIGNAL
, MIDDLE TRACE: OUTPUT SIGNAL FROM THE OPPOSING TERMINAL OF THE SAME LAYER, LOWER TRACE: OUTPUT
FROM A TERMINAL OF ANOTHER LAYER
(25X ENLARGED). THE LEFT MARKER DEFINES THE INPUT TIME REFERENCE.
FURTHER EXPLANATIONS SEE TEXT. ............................................................................................................................ 28
FIGURE 2.7: SINGLE HF-SIGNAL-DE-COUPLER PLUG (HFSD) WITH LEMO OUTPUT AND IN-LINE POTI ............................... 30
FIGURE 2.8: TYPICAL AMPLIFIED PULSE SHAPE FROM THE MCP AFTER PROCESSING WITH AN INVERTING AMPLIFIER (HERE:
ANALOG MONITOR OUTPUT FROM A
ROENTDEK ATR19 MODULE). .................................................................... 32
FIGURE 3.1: THE ATR19 MODULE ....................................................................................................................................... 35
FIGURE 3.2: TOP LID OF ATR19 WITH HOLES TO REACH THE GAIN POTENTIOMETERS. TURNING CLOCKWISE: AMPLIFIER GAIN
IS INCREASED
, TURNING COUNTER CLOCKWISE: GAIN IS DECREASED (FOR ATR19-2 REFER TO CHAPTER 3.6) ........... 36
FIGURE 3.3: ATR19 WITH INPUT SETTINGS FOR DIFFERENTIAL INPUT (NO INPUT JUMPERS SET) .......................................... 37
FIGURE 3.4: ATR19 BASE BOARD WITH INPUT JUMPER SETTINGS FOR SIGNAL INPUT THROUGH THE “+” LEMO INPUT (50Ω
IMPEDANCE TO GROUND
, NON-INVERTING, FOR NEGATIVE SIGNAL INPUT). THE LEVEL CONTROL BOARD WAS REMOVED
HERE FOR BETTER VIEW
. .............................................................................................................................................. 37
FIGURE 3.5: DLATR AMPLIFIER AND CONSTANT FRACTION DISCRIMINATOR BOARDS. ....................................................... 38
FIGURE 3.6: DLATR+ VERSION (LEFT) AND DLATR2.0 (RIGHT) ........................................................................................ 38
FIGURE 3.7: INPUTS, OUTPUTS AND CONTROLS OF THE ATR19 FOR EACH INTERNAL DLATR BOARD ................................ 39
FIGURE 3.8: REAR PANEL OF THE ATR19 (FOR ATR19-2 SEE CHAPTER 3.6) ...................................................................... 41
FIGURE 3.9: ATR19-2B MODULE ......................................................................................................................................... 42
FIGURE 3.10: FRONT AND REAR PANEL OF THE ATR19-2 (LEFT) AND ATR19-2B (RIGHT) .................................................. 43
FIGURE 3.11: TYPICAL AMPLIFIED PULSE SHAPE OF THE MCP AS OBTAINED FROM THE ATR19 ANALOGUE MONITOR OUTPUT.
.................................................................................................................................................................................... 43
FIGURE 3.12: TYPICAL (ANALOGUE) OSCILLOSCOPE SCREEN OUTPUT SHOWING DELAY-LINE SIGNALS FROM A DLATR+
BOARD
: ANALOGUE SIGNALS (MONITOR OUTPUT) ON UPPER TRACE AND THE CORRELATED CFD OUTPUTS (NIM) ON THE
LOWER TRACE
. BOTH TRACES ARE TRIGGERED BY THE NIM SIGNAL. THE PULSE HEIGHT DISTRIBUTION OF THE
ANALOGUE SIGNALS CAN BE SEEN AND ALSO THE EFFECT OF THE THRESHOLD SETTING ON THE REGISTERED EVENTS
(CUT-OFF OF SMALLER SIGNALS NOT BEING REGISTERED). .......................................................................................... 44
FIGURE 3.13: SIGNAL TRACES AS IN FIGURE 3.12, BUT WITH LOW THRESHOLD SETTING VERY CLOSE TO THE NOISE LEVEL
(LEFT). PRE-TRIGGERED SIGNALS ARE PRESENT. THE RIGHT PICTURE SHOWS THE CFD OUTPUT OF AN ERRONEOUS PRE-
TRIGGERED EVENT. ...................................................................................................................................................... 44
FIGURE 3.14: OVERVIEW OF ATR19 SIGNAL OUTPUTS FOR LOW THRESHOLD SETTINGS, TRIGGERED ON THE CFD SIGNAL. 45
FIGURE 3.15: TIME SUM SPECTRA FROM A DELAY-LINE ANODE FOR DIFFERENT THRESHOLD SETTING. LEFT: CLEAN
SPECTRUM
, RIGHT: CONTRIBUTION OF NOISE AND PRE-TRIGGER SIGNALS CAN BE SEEN. SETTING A SOFTWARE GATE ON
THE TIME SUM PEAK MAY STILL PRODUCE RESULTS WITH A DECENT IMAGING PERFORMANCE
. ................................... 45
FIGURE 3.16: CONNECTORS ON THE BACK OF THE SPS1. ..................................................................................................... 46
FIGURE 3.17: HOW TO REMOVE THE INPUT FUSE ................................................................................................................. 48
FIGURE 3.18: FUSE HOLDER ................................................................................................................................................. 48
FIGURE 3.19: ADJUSTING THE OUTPUT VOLTAGES (SPS1 SEEN FROM BOTTOM SIDE) .......................................................... 48
FIGURE 3.20: OPENING THE FUSE HOLDER ........................................................................................................................... 49
FIGURE 3.21: REMOVE THE RIBBON CABLE FROM THE POWER SUPPLY ................................................................................ 50
FIGURE 3.22: OUTPUT FUSES ............................................................................................................................................... 50
FIGURE 3.23: VOLTAGES NEAR THE OUTPUT FUSES ............................................................................................................. 51
FIGURE 3.24: LEDS AT THE FRONT PANEL ........................................................................................................................... 51
FIGURE 4.1: HPTDC8 PCI CARD ........................................................................................................................................ 53
FIGURE 4.2: PCI2PCIE ADAPTER CRATE WITH PCIE CARD FOR THE PC. HERE TWO TDC8HP AND A CLOCK CARD ARE
INSERTED
..................................................................................................................................................................... 54
FIGURE 4.3: HM1-B/T AND HM1-B FRONT PANEL .............................................................................................................. 55
FIGURE 4.4: PCI INTERFACE CARD ...................................................................................................................................... 55
FIGURE 4.5: TDC8PCI2 BOARD ........................................................................................................................................... 55
FIGURE 4.6: SIDE AND INPUT PANEL VIEW OF THE HM1 - I/O-BOARD (PCI) ........................................................................ 56
FIGURE 4.7: SIDE AND INPUT PANEL VIEW OF THE HM1 - I/O-BOARD (ISA) ........................................................................ 57
FIGURE 4.8: SCREEN AFTER STARTING THE COBOLDPC 2011 R3 PROGRAM ........................................................................ 59
FIGURE 5.1: 2X4KV POWER SUPPLY (FRONT PANEL) .......................................................................................................... 69
FIGURE 5.2: 2X4KV POWER SUPPLY (SIDE-PANEL) .............................................................................................................. 70
FIGURE 5.3: 2X4KV POWER SUPPLY (REAR-PANEL) ............................................................................................................ 70
FIGURE 5.4: BIASET3 WITH SPS2 AND ONE HV2/4 MODULE (CORRESPONDS TO BIASET3-2) .......................................... 71
FIGURE 5.5: SPS2 FRONT AND REAR PANEL WITH CONNECTION CABLE TO HV2/4 MODULE (NOT SHOWN). ......................... 72
Page 82 of 83 MCP Delay Line Detector Manual (11.0.1304.1)
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