© by SEMIKRON / 2017-09-07 / Technical Explanation / SKiiP
4
Page 63/73
7.10 Switching operation and current sharing between paralleled half bridge modules
The SKiiP4 is made for switching application. However since dynamic processes are occurring in the utilized
semiconductors, e.g. IGBT and Diodes a certain minimum time shall be considered before a next switching
operation can be started. Hence this minimum conduction time or pulse width for the IGBT and the Diode
shall be kept by the application software to ensure that all transient processes in the semiconductors have
been finished and no undesired tripping or oscillation might happen. For further details please refer to
application handbook section 2.3.3.2. For the SKiiP4 the following minimum conduction times shall be kept:
• For 1200V SKiiP4
o t
min
(IGBT) > 2µs
o t
min
(Diode) > 3µs
• For 1700V SKiiP4
o t
min
(IGBT) > 2µs
o t
min
(Diode) > 5µs
The busbar has to be designed symmetrically to make sure that the current sharing is equal. Unequal
current sharing can overload single half bridge modules and leads to imbalance during switching operation
as well as in steady state conduction which can finally destroy the power section.
Symmetrical AC and DC-link design leads to equal stray inductances between the half bridge modules
which ensures equal commutation and current sharing. Each half bridge module has to have the same stray
inductance to the DC-link capacitors.
The recommended AC connection is shown in Figure 7.17.The current sharing should be measured in the
design phase by “double pulse testing” (see AN-7006) and in the final design under real operation
conditions. This can be done e.g. by Rogowski current sensors which are located around the DC+ and DC-
terminals.
7.11 Paralleling of SKiiP
®
4
The parallel operation of SKiiP 4’s requires the following considerations and features:
• Common error management for all paralleled SKiiP
®
4 can be realized using the HALT signal
• Monitoring of analogue signals, e.g. temperature or current
• one power supply should be used for all subsystems
By using paralleled SKiiPs it has to be made sure that no SKiiP will be overloaded, e.g. by current
imbalance. Such an inhomogeneous current can be caused by different output voltages of the paralleled
inverters which could be a consequence of:
• different propagation time of driver board signals
• different switching times of power semiconductors
• tolerance of forward voltage drop of IGBT or diodes
• different DC link voltage levels
• different cooling conditions of paralleled half bridges (e.g. in air cooled applications with thermal
stacking)
• different external impedance
A suitable parallel connection of all AC-terminals can be achieved by an additional flexible cross
connector directly mounted on the SKiiP AC terminals (marked with an arrow in Figure 7.17).
Please note that the current rating of this bar must not be very high, because there is no load current
flowing in this bar. There are only high frequency currents flowing. Thus the flexibility can be achieved
by using a comparatively thin material.
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