© by SEMIKRON / 2017-09-07 / Technical Explanation / SKiiP
4
Page 69/73
List of figures:
Figure 2. 1: SKiiP
®
4 – 4 fold ............................................................................................................. 5
Figure 2.2: Half bridge definition ....................................................................................................... 5
Figure 2.3: Half bridge “exploded assembly view” ............................................................................... 6
Figure 2.4: Main terminals construction principle ................................................................................. 7
Figure 4.1: Grounded delta grid ....................................................................................................... 11
Figure 4.2: Star grounded circuit network (690V-TN-grid) .................................................................. 11
Figure 4.3: Implementation of additional basic isolation between SKiiP
®
4 driver interface and controller
board ........................................................................................................................................... 13
Figure 5.1: Gate Driver Board block diagram ..................................................................................... 15
Figure 5.2: Gate Driver Interface ..................................................................................................... 16
Figure 5.3: SKiiP
®
4 - connector D-Sub 25 pin, male plug, vertical, top view .......................................... 16
Figure 5.4: Overview schematics SKiFace interface (CMN_GPIO1/2 and CMN_HALT are not shown .......... 19
Figure 5.5: TOP/BOT PWM Signal Input ............................................................................................ 21
Figure 5.6: Threshold level for HB_TOP and HB_BOT .......................................................................... 21
Figure 5.7: Schematic view of the analogue output signals ................................................................. 22
Figure 5.8: Application example – symmetric wired differential amplifier. Terminal description HB_I and
HB_I_GND for current measurement ................................................................................................ 23
Figure 5.9: Application example of the HALT signal processing for separated SKiiP
®
4 systems ................. 25
Figure 5.10: Application example of the CMN_GPIO1 (inverted HALT signal) as error output signal .......... 26
Figure 5.11: CAN-Interface ............................................................................................................. 27
Figure 5.12: CAN – application example for several SKiiP.................................................................... 27
Figure 5.13: Prevention of ground loops by differential amplifier circuitry ............................................. 29
Figure 5.14: Ground and shield connection. Principle schematics for Ground and shield connection. Principle
equivalent circuit of switching signal inputs ....................................................................................... 30
Figure 5.15: Ground and shield connection. Principle equivalent circuit for analogue output signals
(Example: Temperature output) ...................................................................................................... 30
Figure 5.16: Connection of reserved and not used signals at the user controller board ........................... 31
Figure 5.17: Power-On-Reset timing diagramm ................................................................................ 32
Figure 5.18: Short pulse suppression .............................................................................................. 33
Figure 5.19 : Turn-off speed scenarios ............................................................................................. 33
Figure 5.20: Switching frequency range ........................................................................................... 36
Figure 5.21: Timing diagram for the TOP/BOT overlapping error processing (t<3µs) ............................. 36
Figure 5.22: Timing diagram for the HB_TOP/HB_BOT overlapping error processing (t>3µs) .................. 37
Figure 5.23: No short circuit .......................................................................................................... 38
Figure 5.24: Short circuit during operation ....................................................................................... 38
Figure 5.25: Short circuit during turn on .......................................................................................... 38
Figure 5.26: Characteristics between current and the voltage at HB_I, SKiiP
®
4 3-fold ........................... 38
Figure 5.27: Characteristic between current and the voltage at HB_I, SKiiP
®
4 4-fold ............................. 40
Figure 5.28: Characteristic between current and the voltage at HB_I, SKiiP
®
4 6-fold ............................. 40
Figure 5.29: Bode diagram of the AC-current measurement at the SKiiP4 interface ............................... 41
Figure 5.30: Compensation principle of SKiiP
®
4 current sensor ........................................................... 41
Figure 5.31: Characteristic between DCB-sensor temperature and the voltage at CMN_TEMP .................. 42
Figure 5.32: DC link voltage sensor output 1200V system .................................................................. 44
Figure 5.33: DC-link voltage sensor output 1700V system .................................................................. 44
Figure 5.34: Bode diagram of the DC-link voltage measurement at the SKiiP4 interface ......................... 45
Figure 6.1: Maximum forces at the main terminals............................................................................. 47
Figure 6.2: AC connection .............................................................................................................. 48
Figure 7.1: Safe Operating Area for standard SKiiP
®
4 ......................................................................... 49
Figure 7.2: Definition of thermal resistances ..................................................................................... 50
Figure 7.3: Sensor position in SKiiP
®
4 GB (6fold, 4fold, 3fold) with proposed cooling (water inlet) direction51
Figure 7.4: SKiiP
®
4 mechanical drawing ........................................................................................... 52
Figure 7.5: SKiiP
®
4 side cap mechanical drawing ............................................................................... 53
Figure 7.6: Description of fitting ISO 1179-2 — G 1/2 A — L ............................................................... 53
Figure 7.7: Description of fitting ISO 1179-3 — G 1/2 A — G .............................................................. 54
Figure 7.8: Graphic presentation of the electrical connections by the IVT procedure ............................... 55
Figure 7.9: Graphic schematic of the wind mill .................................................................................. 57
Figure 7.10: Graphic presentation of SKiiP
®
4 behaviour without FRT-function activated in case of
overcurrent ................................................................................................................................... 57
Figure 7.11: Graphic presentation of SKiiP
®
4 behaviour with FRT-function activated in case of overcurrent58
Figure 7.12: Graphic presentation of the driver processing in FRT-case ................................................ 58
Figure 7.13: SOA for SKiiP
®
4 Solar .................................................................................................. 59
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