STM32F30xx Standard Peripheral Library
__IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S
mode),Address offset: 0x18 */
uint16_t RESERVED6;/*!< Reserved, 0x1A
*/
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register,
Address offset: 0x1C */
uint16_t RESERVED7;/*!< Reserved, 0x1E
*/
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address
offset: 0x20 */
uint16_t RESERVED8;/*!< Reserved, 0x22
*/
} SPI_TypeDef;
The register names are the register acronyms written in upper case for each peripheral.
RESERVEDi (I being an integer that indexes the reserved field) indicates a reserved field.
Each peripheral has several dedicated registers which contain different flags. Registers are
defined within a dedicated structure for each peripheral. Flags are defined as acronyms
written in upper case and preceded by „PPP_FLAG_‟. The flag definition is adapted to each
peripheral case and defined in stm32f30x_ppp.h.
Peripheral declaration
All peripherals are declared in stm32f30x.h. The following example shows the declaration
of the SPI peripheral:
...
/*!< Peripheral base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000)
...
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
...
/*!< APB1 peripherals base address */
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
...
/*!< APB2 peripherals base address */
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
...
/*!< Peripheral Declaration */
...
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
...
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
SPIx_BASE is the base address of a specific SPI and SPIx is a pointer to a register
structure that refers to a specific SPI.
The peripheral registers are accessed as follows:
SPI1->CR1 = 0x0001;
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