ST STM32F31xx

UM1581
Reset and clock control (RCC)
DocID023800 Rev 1
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18 Reset and clock control (RCC)
18.1 RCC Firmware driver registers structures
18.1.1 RCC_TypeDef
RCC_TypeDef is defined in the stm32f30x.h
Data Fields
 __IO uint32_t CR
 __IO uint32_t CFGR
 __IO uint32_t CIR
 __IO uint32_t APB2RSTR
 __IO uint32_t APB1RSTR
 __IO uint32_t AHBENR
 __IO uint32_t APB2ENR
 __IO uint32_t APB1ENR
 __IO uint32_t BDCR
 __IO uint32_t CSR
 __IO uint32_t AHBRSTR
 __IO uint32_t CFGR2
 __IO uint32_t CFGR3
Field Documentation
 __IO uint32_t RCC_TypeDef::CR
 RCC clock control register, Address offset: 0x00
 __IO uint32_t RCC_TypeDef::CFGR
 RCC clock configuration register, Address offset: 0x04
 __IO uint32_t RCC_TypeDef::CIR
 RCC clock interrupt register, Address offset: 0x08
 __IO uint32_t RCC_TypeDef::APB2RSTR
 RCC APB2 peripheral reset register, Address offset: 0x0C
 __IO uint32_t RCC_TypeDef::APB1RSTR
 RCC APB1 peripheral reset register, Address offset: 0x10
 __IO uint32_t RCC_TypeDef::AHBENR
 RCC AHB peripheral clock register, Address offset: 0x14
 __IO uint32_t RCC_TypeDef::APB2ENR
 RCC APB2 peripheral clock enable register, Address offset: 0x18
 __IO uint32_t RCC_TypeDef::APB1ENR
 RCC APB1 peripheral clock enable register, Address offset: 0x1C
 __IO uint32_t RCC_TypeDef::BDCR
 RCC Backup domain control register, Address offset: 0x20
 __IO uint32_t RCC_TypeDef::CSR
 RCC clock control & status register, Address offset: 0x24
 __IO uint32_t RCC_TypeDef::AHBRSTR
 RCC AHB peripheral reset register, Address offset: 0x28
 __IO uint32_t RCC_TypeDef::CFGR2