ST STM32F31xx

UM1581
Reset and clock control (RCC)
DocID023800 Rev 1
337/584
 RCC_IT_HSERDY : HSE ready interrupt
 RCC_IT_PLLRDY : PLL ready interrupt
 RCC_IT_CSS : Clock Security System interrupt
Return values
 None.
Notes
 None.
18.3 RCC Firmware driver defines
18.3.1 RCC
RCC
RCC_ADC_clock_source
 #define: RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
 #define: RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
 #define: RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
 #define: RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
 #define: RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
 #define: RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
 #define: RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
 #define: RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)